Circuit for selecting/deselecting a bitline of a non-volatile memory

A memory comprising:

• an array of non-volatile memory cells;
• and
• a plurality of bit-line selection circuits connected to said array of non-volatile memory cells, each bit line selection circuit comprising
• a decoding line including a regulated voltage node and a programming voltage node generating a programming voltage for a corresponding non-volatile memory cell, said decoding line comprising at least one input transistor connected to the regulated voltage node and being controlled by an enable/disable signal,
• a dummy line identical to said decoding line and being controlled by the enable/disable signal,
• an equalization circuit connected between said decoding and dummy lines for setting a current in said dummy line equal to a current in said decoding line, and
• a regulating circuit for regulating the programming voltage generated at the programming voltage node of said decoding line by compensating for differences between a programming voltage and the reference voltage, said regulating circuit having a first input for receiving the reference voltage, a second input for receiving a sensed voltage on the programming voltage node in said dummy line, and an output for providing the enable/disable signal.

A memory comprising:

• a charge pump providing a regulated voltage to a regulated voltage node;
• an array of memory cells arranged in rows and columns;
• and
• a plurality of bit-line selection circuits connected to the columns of said array of memory cells, each bit line selection circuit comprising
• a decoding line including the regulated voltage node and a programming voltage node and generating a programming voltage for a memory cell in a corresponding bit line, said decoding line comprising at least one input transistor connected to the regulated voltage node and being controlled by an enable/disable signal,
• a dummy line identical to said decoding line and being controlled by the enable/disable signal,
• at least one current mirror connected between said decoding and dummy lines for setting a current in said dummy line equal to a current in said decoding line, and
• an error amplifier having a first input for receiving a reference voltage, a second input for receiving a sensed voltage on the programming voltage node in said dummy line, and an output for providing the enable/disable signal which compensates for differences between the programming voltage and the reference voltage.