Memory devices using tri-state buffers to discharge data lines, and methods of operating same
AssigneeSamsung Electronics Co., Ltd.
InventorsSang-Wan Nam, Seung-Keun Lee
Life of this patent
Estimating the term…
Abstract
A memory device includes a sense amplifier circuit, a tri-state buffer, a data latch circuit and a data line. The sense amplifier circuit senses and amplifies a current of a memory cell. The tri-state buffer receives an output of the sense amplifier circuit. The data latch circuit latches an output of the tri-state buffer. The data line connects the tri-state buffer and the data latch circuit. The memory device removes charge on the data line using a latch enable signal, which is applied to the tri-state buffer before a read operation.
Claims18
A memory device comprising:
- a sense amplifier circuit that is configured to sense and amplify a current of a memory cell;
- a tri-state buffer that is configured to receive an output of the sense amplifier circuit;
- a data latch circuit that is configured to latch an output of the tri-state buffer;
- and
- a data line connecting the tri-state buffer and the data latch circuit, wherein the tri-state buffer is configured to discharge the data line in response to a latch enable signal after a bitline discharge circuit discharges a bitline that is connected to the memory cell.
A memory device comprising:
- a memory cell connected to a bitline;
- a discharging circuit that is configured to discharge the bitline;
- a sense amplifier circuit that is configured to sense and amplify a current of the bitline;
- a tri-state buffer that is configured to receive an output of the sense amplifier circuit;
- a data latch circuit that is configured to latch an output of the tri-state buffer;
- and
- a data line connecting the tri-state buffer and the data latch circuit, wherein the tri-state buffer is configured to discharge the data line in response to the latch enable signal after the bitline discharge circuit discharges the bitline.
A memory device comprising:
- a memory cell;
- a sense amplifier circuit that is configured to sense and amplify a current of the memory cell;
- a data latch circuit;
- and
- a tri-state buffer that is configured to connect an output of the sense amplifier circuit to an input of the data latch circuit;
- wherein the tri-state buffer and the data latch circuit are both responsive to a common control signal;
- and
- a data line connecting the tri-state buffer and the data latch circuit, wherein the tri-state buffer is configured to discharge the data line in response to the common control signal after a bitline discharge circuit discharges a bitline that is connected to the memory cell.
A method of operating a memory device that includes a memory cell, a sense amplifier circuit that is configured to sense and amplify a current of the memory cell, a data latch circuit and a tri-state buffer that is configured to connect an output of the sense amplifier circuit to an input of the data latch circuit, the method comprising:
- placing the tri-state buffer in a reduced impedance state to discharge the input of the data latch circuit in response to a common control signal that is applied to both the tri-state buffer and the data latch circuit;
- and
- discharging a data line that connects the tri-state buffer and the data latch circuit in response to the common control signal after a bitline discharge circuit discharges a bitline that is connected to the memory cell.
Dependencies are inferred from the claim text.