Multi-domain liquid crystal display and a thin film transistor substrate of the same

A thin film transistor array panel comprising:

• an insulating substrate;
• a gate wire formed on the insulating substrate and including first and second gate electrodes and a plurality of gate lines;
• a storage electrode wire formed on the insulating substrate and including a plurality of storage electrode lines and a plurality of storage electrodes;
• a gate insulating layer formed on the gate wire and the storage electrode wire;
• a semiconductor layer formed on the gate insulating layer;
• a data wire formed on the semiconductor layer and including a plurality of data lines intersecting the gate lines, a plurality of first source electrodes connected to the data lines, a plurality of first drain electrodes opposite the first source electrodes with respect to the first gate electrodes, a plurality of second source electrodes electrically connected to the storage electrode wire, and a plurality of second drain electrodes opposite the second source electrodes with respect to the second gate electrodes;
• a direction control electrode connected to the second drain electrode;
• a passivation layer formed on the data wire and the direction control electrode and having a plurality of contact holes;
• and
• a pixel electrode formed on the passivation layer, having a plurality of cutouts, and electrically connected to the first drain electrodes through the contact holes.

A liquid crystal display comprising:

• a first insulating substrate;
• a plurality of first signal lines formed on the first insulating substrate;
• a plurality of second signal lines formed on the first insulating substrate, insulated from the first signal lines, and intersecting the first signal lines;
• a plurality of third signal lines formed on the first insulating substrate, insulated from the second signal lines, and intersecting the second signal lines;
• a plurality of pixel electrodes provided on the respective pixel areas defined by the intersections of the first and the second signal lines, each pixel electrode having a cutout;
• a plurality of direction control electrodes provided on the respective pixel areas defined by the intersections of the first and the second signal lines;
• a plurality of switching elements, each first switching element connected to one of the first signal lines, one of the second signal lines, and one of the pixel electrodes;
• a plurality of second thin film transistors, each second switching element connected to one of the first signal lines, one of the third signal lines, and one of the direction control electrodes;
• a second insulating substrate opposite the first insulting substrate;
• a common electrode formed on the second insulating substrate;
• and
• a liquid crystal layer interposed between the first insulating substrate and the second insulating substrate.

A thin film transistor array panel comprising:

• an insulating substrate;
• a gate wire formed on the insulating substrate;
• a storage electrode wire formed on the insulating substrate;
• a gate insulating layer formed on the gate wire and the storage electrode wire;
• a data wire formed on the gate insulating layer including three layers an amorphous silicon layer, a doped amorphous silicon layer, and a metal layer;
• a direction control electrode formed on the gate insulating layer, including three layers an amorphous silicon layer, a doped amorphous silicon layer, and a metal layer, and electrically connected to the second drain electrode;
• a passivation layer formed on the data wire and the direction control electrode and having a plurality of contact holes;
• and
• a pixel electrode formed on the passivation layer, having a plurality of cutouts, and electrically connected to the data wire through the contact holes.

A method of manufacturing a thin film transistor array panel, comprising:

• forming a gate wire and a storage electrode wire;
• depositing a gate insulating layer, an amorphous silicon layer, a contact layer, and a metal conductive layer;
• patterning the amorphous silicon layer, the contact layer, and the metal conductive layer to form a data wire, a direction control electrode, and a channel portion of a thin film transistor;
• forming a passivation layer on the channel portion;
• forming a pixel electrode on the passivation layer;
• forming a plurality of connecting members on the passivation layer;
• forming a plurality of source electrodes electrically connected to the storage electrode wire;
• and
• connecting the source electrodes and the storage electrode wire through contact holes provided at the passivation layer and the gate insulating layer.