Locking display pixel clock to input frame rate
AssigneeGreenforest Consulting, Inc
InventorsJames Y. Louie, Menq Yu Shyu
Life of this patent
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Abstract
To match the output frame rates to the input frame rates, a display clock signal is generated that has a frequency locked to the frequency of a reference clock signal. To generate the display clock signal, the period of the vertical incoming data clock is measured using the reference clock signal. The number of pixels disposed in the output frames is subsequently divided by the measured period. A fractional-N phase-locked loop circuit is adapted to multiply the result of the division with the frequency of the reference clock signal to generate the display clock signal. The display clock signal is also locked to the reference clock signal.
Claims12
An integrated circuit comprising:
- a first block configured to determine a period of an input clock signal using a reference clock signal;
- a second block configured to receive the determined period and to generate a multiplier signal carrying a multiplier value;
- and
- a third block configured to multiply the reference clock signal frequency by the multiplier signal to generate a output clock signal, said third block further configured to lock the output clock signal to the reference clock signal, wherein said input clock signal is used for vertical synchronization of input frames.
A method of locking an output clock signal to an input clock signal, the method comprising:
- determining a period of the input clock signal using a reference clock signal;
- generating a multiplier signal carrying a multiplier value using the determined period;
- multiplying the reference clock signal frequency by the multiplier signal to generate the output clock signal;
- and
- locking the output clock signal to the reference clock signal, wherein said input clock signal is used for vertical synchronization of input frames.
Dependencies are inferred from the claim text.