PLL clock generator circuit and clock generation method
AssigneeFujitsu Limited
InventorKoji Okada
Life of this patent
Estimating the term…
Abstract
A clock generator circuit is provided wherein a comparison clock signal is generated by comparing a standard clock signal and an operating clock signal. The comparison clock signal is converted into a current signal. The current signal is converted to multiple current signals and an operating clock signal having multiple varying frequencies is generated based on the multiple current signals.
Claims18
A clock generator circuit comprising:
- a phase comparator receiving a standard clock signal and an operating clock signal and generating an output signal;
- and
- a voltage controlled oscillator generating the operating clock signal based on the output signal of the phase comparator,
- wherein the voltage controlled oscillator comprises:
- a voltage current converter converting a voltage signal into a current signal;
- a current D/A converter fluctuating the current signal based on a digital signal;
- and
- a current controlled oscillator oscillating the operating clock signal of which frequency corresponds to each of the variable current signals;
- wherein the current DA converter has a plurality of current sources including current mirror circuits.
A clock generator circuit for generating an operating clock based on a current signal generated based on a result of a comparison between a standard clock signal and a comparison clock signal comprising:
- a first circuit generating a plurality of current signals;
- and
- a second circuit generating a plurality of operating clock signals of which frequencies are different with each other based on the plurality of current signals,
- wherein the first circuit comprises a current D/A converter that is controlled by a digital signal;
- wherein the current DA converter has a plurality of current sources including current mirror circuits.
A clock generator circuit comprising:
- a first clock generator part generating a first clock signal, wherein the first clock generator part comprises a phase comparator for comparing a standard clock signal and an operating clock signal, a voltage current converter converting a signal based on the comparison results into a current signal and a first current controlled oscillator generating the first clock signal based on the current signal;
- and
- a second clock generator part generating a second clock signal, wherein the second clock generator part comprises a current D/A converter converting the current signal into variable current signals based on a digital signal for spreading spectrum and a second current controlled oscillator oscillating the second clock signal of which frequency corresponds to each of the variable current signals;
- wherein the current DA converter has a plurality of current sources including current mirror circuits.
A clock generator circuit comprising:
- a first circuit generating a first clock signal of a frequency spectrum containing N number of peaks (N is an integer);
- and
- a second circuit generating a second clock signal of a frequency containing a frequency spectrum with M number of peaks (M is an integer that is greater than 1, M>N) on the basis of a current signal generated based on a digital signal for spreading spectrum, the digital signal for spreading spectrum is based on a comparison result of comparing a standard clock signal and an operating clock signal;
- wherein the current DA converter has a plurality of current sources including current mirror circuits.
A PLL circuit comprising:
- a phase comparator receiving and comparing a standard clock signal and an operating clock signal;
- a charge pump supplying an output signal based on the comparison;
- a voltage controlled oscillator outputting the operating clock signal based on the output signal of the charge pump;
- wherein the voltage controlled oscillator comprises a voltage current converter that converts a voltage signal into a current signal;
- a current D/A converter that changes the current signal into a variable current signal based on a digital signal;
- and
- a current controlled oscillator that oscillates the operating clock signal based on the variable current signal;
- wherein the current DA converter has a plurality of current sources including current mirror circuits.
A clock generation method comprising the steps of:
- comparing a standard clock signal and an operating clock signal;
- converting the results of the comparison into a current signal;
- using a current D/A converter to change the current signal into variable current signals based on a digital control signal;
- and
- outputting the operating clock signal with varying frequencies based on the variable current signal;
- wherein the current DA converter has a plurality of current sources including current mirror circuits.
Dependencies are inferred from the claim text.