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US 7,253,674 B1Granted
Output clock phase-alignment circuit
AssigneeLattice Semicondutor Corporation
InventorsPhillip L. Johnson, Gary P. Powell, Harold N. Scholz
Life of this patent
Estimating the term…
Abstract
A clock generator has a reset circuit and (at least) two dividers, where each divider divides a reference clock signal by a divisor value to generate an output clock signal. The reset circuit generates reset signals for the dividers, where the reset signals are delayed relative to one another by a selected number of reference clock cycles, such that the dividers generate output clock signals having a desired phase offset between them.
Claims24
A method for generating two or more output clock signals, the method comprising:
- receiving a control signal corresponding to a specified number of reference clock cycles, wherein the control signal has any one of a plurality of different values;
- delaying a second reset signal relative to a first reset signal based on the specified number of reference clock cycles;
- dividing a first reference clock signal based on a first divisor value to generate a first output clock signal based on the first reset signal;
- and
- dividing a second reference clock signal based on a second divisor value to generate a second output clock signal based on the second reset signal, wherein (1) the specified number of reference clock cycles is independent of the first and second divisor values and (2) phase offset between the first and second output clock signals is a function of the specified number of reference clock cycles and at least one of the first and second divisor values.
2 more elements
A clock generator for generating two or more output clock signals, the clock generator comprising:
- a first divider adapted to divide a first reference clock signal based on a first divisor value to generate a first output clock signal;
- and
- a second divider adapted to divide a second reference clock signal based on a second divisor value to generate a second output clock signal;
- and
- a reset circuit adapted to (1) receive a control signal corresponding to a specified number of reference clock cycles, wherein the control signal has any one of a plurality of different values, and (2) generate a first reset signal for resetting the first divider and a second reset signal for resetting the second divider, wherein:
- the specified number of reference clock cycles is independent of the first and second divisor values;
- the second reset signal is delayed relative to the first reset signal based on the specified number of reference clock cycles;
- and
- phase offset between the first and second output clock signals is a function of the specified number of reference clock cycles and at least one of the first and second divisor values.
6 more elements
An integrated circuit having a clock generator for generating two or more output clock signals, the clock generator comprising:
- a first divider adapted to divide a first reference clock signal based on a first divisor value to generate a first output clock signal;
- and
- a second divider adapted to divide a second reference clock signal based on a second divisor value to generate a second output clock signal;
- and
- a reset circuit adapted to (1) receive a control signal corresponding to a specified number of reference clock cycles, wherein the control signal has any one of a plurality of different values, and (2) generate a first reset signal for resetting the first divider and a second reset signal for resetting the second divider, wherein:
- the specified number of reference clock cycles is independent of the first and second divisor values;
- the second reset signal is delayed relative to the first reset signal based on the specified number of reference clock cycles;
- and
- phase offset between the first and second output clock signals is a function of the specified number of reference clock cycles and at least one of the first and second divisor values.
6 more elements
A method for generating two or more output clock signals, the method comprising:
- delaying a second reset signal relative to a first reset signal based on a specified number of reference clock cycles;
- dividing a first reference clock signal based on a first divisor value to generate a first output clock signal based on the first reset signal;
- and
- dividing a second reference clock signal based on a second divisor value to generate a second output clock signal based on the second reset signal, wherein:
- phase offset between the first and second output clock signals is a function of the specified number of reference clock cycles and at least one of the first and second divisor values;
- the first and second reset signals are generated by a reset circuit based on an input reset signal;
- the first output clock signal is generated by a first divider;
- the second output clock signal is generated by a second divider;
- the reset circuit comprises a multiplexer and a series of delay elements;
- the input reset signal is applied to a first delay element in the series;
- the first reset signal is output from one of the delay elements in the series;
- and
- the multiplexer receives outputs from two or more of the delay elements in the series and selects one of the delay element outputs as the second reset signal.
10 more elements
A clock generator for generating two or more output clock signals, the clock generator comprising:
- a first divider adapted to divide a first reference clock signal based on a first divisor value to generate a first output clock signal;
- and
- a second divider adapted to divide a second reference clock signal based on a second divisor value to generate a second output clock signal;
- and
- a reset circuit adapted to generate a first reset signal for resetting the first divider and a second reset signal for resetting the second divider, wherein:
- the second reset signal is delayed relative to the first reset signal based on a specified number of reference clock cycles;
- phase offset between the first and second output clock signals is a function of the specified number of reference clock cycles and at least one of the first and second divisor values;
- the reset circuit is adapted to generate the first and second reset signals based on an input reset signal;
- the reset circuit comprises a multiplexer and a series of delay elements;
- a first delay element in the series is adapted to receive the input reset signal;
- one of the delay elements in the series is adapted to output the first reset signal;
- and
- the multiplexer is adapted to receive outputs from two or more of the delay elements in the series and selects one of the delay element outputs as the second reset signal.
10 more elements
An integrated circuit having a clock generator for generating two or more output clock signals, the clock generator comprising:
- a first divider adapted to divide a first reference clock signal based on a first divisor value to generate a first output clock signal;
- and
- a second divider adapted to divide a second reference clock signal based on a second divisor value to generate a second output clock signal;
- and
- a reset circuit adapted to generate a first reset signal for resetting the first divider and a second reset signal for resetting the second divider, wherein:
- the second reset signal is delayed relative to the first reset signal based on a specified number of reference clock cycles;
- phase offset between the first and second output clock signals is a function of the specified number of reference clock cycles and at least one of the first and second divisor values;
- the reset circuit is adapted to generate the first and second reset signals based on an input reset signal;
- the reset circuit comprises a multiplexer and a series of delay elements;
- a first delay element in the series is adapted to receive the input reset signal;
- one of the delay elements in the series is adapted to output the first reset signal;
- and
- the multiplexer is adapted to receive outputs from two or more of the delay elements in the series and selects one of the delay element outputs as the second reset signal.
10 more elements
Dependencies are inferred from the claim text.