Multi-phase clock generator and generating method for network controller
AssigneeRealtek Semiconductor Corp.
InventorShian-Ru Lin
Life of this patent
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Abstract
The present invention discloses a multi-phase clock generator of a network controller for generating a set of multi-phase clocks, and a method thereof. The multi-phase clock generator includes a first gating element and a second gating element. The first gating element operates according to a first control clock and generates a first output clock of the set of multi-phase clocks according to an input clock. The second gating element operates according to a second control clock and generates a second output clock of the set of multi-phase clocks according to the first output clock. The second control clock is an inverted signal of the first control clock.
Claims20
A multi-phase clock generator set in a network controller, for generating a set of multi-phase output clocks, the multi-phase clock generator comprising:
- a first gating element operating according to a first control clock and generating a first output clock of the set of multi-phase output clocks according to an input clock, the input clock being selected from a first reference clock and a second reference clock, frequencies of the first and second reference clocks being smaller than a frequency of the first control clock;
- and
- a second gating element coupled to the first gating element, operating according to a second control clock and generating a second output clock of the set of multi-phase output clocks according to the first output clock.
A method utilized in a network controller for generating a set of multi-phase output clocks, the method comprising:
- receiving a first reference clock and a second reference clock;
- outputting the first reference clock or second reference clock to be an input clock according to a mode control signal, the mode control signal corresponding to a first network transmission mode or a second network transmission mode;
- gating the input clock according to a first control clock to generate a first output clock of the set of multi-phase output clocks;
- and
- gating the first output clock according to a second control clock to generate a second output clock of the set of multi-phase output clocks.
Dependencies are inferred from the claim text.