Phase synchronization circuit and semiconductor integrated circuit

A phase synchronization circuit which delays transition timing of a third clock signal to generate a fourth clock signal based on a transition timing difference between a first clock signal and a second clock signal, said circuit comprising:

• a first delay line which includes a plurality of delay elements and to which said first clock signal is inputted;
• a phase comparator line which includes a plurality of phase comparators in accordance with said first delay line and to which a signal from said first delay line and said second clock signal are inputted so as to measure a transition timing difference between said first clock signal and said second clock signal;
• and
• a second delay line which includes a plurality of delay elements in accordance with said first delay line and to which a signal from said phase comparator line and said third clock signal are inputted,
• wherein a ratio of delay time of the delay elements in the first delay line to delay time of the delay elements in the second delay line is constant,
• wherein a value of said ratio of delay time of said delay elements is any value other than 1.

A phase synchronization circuit which delays transition timing of a third clock signal to generate a fourth clock signal based on a transition timing difference between a first clock signal and a second clock signal, said circuit comprising:

• a first delay line which includes a plurality of delay elements having different delay times and to which said first clock signal is inputted;
• a phase comparator line which includes a plurality of phase comparators in accordance with said first delay line and to which a signal from said first delay line and said second clock signal are inputted so as to measure a transition timing difference between said first clock signal and said second clock signal;
• and
• a second delay line which includes a plurality of delay elements having different delay times in accordance with said first delay line and to which a signal from said phase comparator line and said third clock signal are inputted,
• wherein the delay time of said plurality of delay elements in said first delay line and said second delay line is fixed, and a ratio of delay time of the delay elements in the first delay line to delay time of the delay elements in the second delay line is constant,
• wherein, in said first delay line, delay time of the delay element on a first tier side where said first clock signal reaches earlier is short and delay time of the delay element on a latter tier side where said first clock signal reaches later is long, and
• a value of said ratio of delay time of said delay elements is any value other than 1.