Clock frequency divider circuit and method of dividing clock frequency
AssigneeElite Semiconductor Memory Technology Inc.
InventorsMin-Chung Chou, Shu-Fang Wu
Life of this patent
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Abstract
A clock frequency divider circuit and method of dividing a clock frequency are provided. The clock frequency divider circuit includes a first flip-flop circuit, a second flip-flop circuit, a third flip-flop circuit, a first logic control unit and a second logic control unit, wherein the first flip-flop circuit has two clock input terminals connected to the second and third flip-flop circuits respectively and two control signal input terminals connected to the first and second logic control units respectively. The second and third flip-flop circuits count rising edges and falling edges of an input frequency under control of the first and second flip-flop circuits and accordingly, symmetric output signals are output from the first flip-flop circuit.
Claims20
A clock frequency divider circuit, comprising:
- a first flip-flop circuit, having first and second clock input terminals and first and second control signal input terminals;
- a second flip-flop circuit, having a third control signal input terminal and an output terminal connected to the first clock input terminal;
- a third flip-flop circuit, having a fourth control signal input terminal and an output terminal connected to the second clock input terminal;
- a first logic control unit, having an output terminal connected to the first control signal input terminal of the first flip-flop circuit and the third control signal input terminal of the second flip-flop circuit;
- and
- a second logic control unit, having an output terminal connected to the fourth control signal input terminal of the third flip-flop circuit and the second control signal input terminal of the first flip-flop circuit.
A method of dividing a frequency of a clock, comprising the steps of:
- functioning an external clock and an output signal from a first flip-flop circuit as inputs of a first logic control unit;
- controlling the rest flip-flop circuit and a second flip-flop circuit by the first logic control unit;
- functioning the external clock and the output signal from the first flip-flop circuit as inputs of a second logic control unit;
- and
- controlling the first flip-flop circuit and a third flip-flop circuit by the second logic control unit.
Dependencies are inferred from the claim text.