Method and apparatus for a configurable latch
AssigneeXilinx, Inc.
InventorsTim Tuan, Sean W. Kao
Life of this patent
Estimating the term…
Abstract
A configurable latch is implemented using a configurable pulse generator and a level sensitive (LS) latch. The configurable pulse generator produces either a pulse signal that is aligned with the input clock edge, or simply provides the input clock signal to its output in response to a pulse generator control signal. If a pulse signal is provided to the latch, then edge triggered (ET) latch operation is effected within the latch. If, on the other hand, a clock signal is provided to the latch, then LS latch operation is effected within the latch. Thus, configuration of latch operation is established in response to the type of clock signal that is provided to the latch.
Claims18
A configurable latch, comprising:
- a pulse generator coupled to receive a clock input signal and a pulse mode signal, the pulse generator adapted to provide a clock output signal having a programmable duty cycle in response to a logic level of the pulse mode signal;
- and
- a level sensitive (LS) latch coupled to receive the clock output signal, the LS latch adapted to operate as an edge triggered (ET) latch in response to a first duty cycle of the clock output signal and adapted to operate as an LS latch in response to a second duty cycle of the clock output signal,
- wherein the pulse generator comprises a reset circuit coupled to receive a reset value and a reset signal and adapted to drive an output of the LS latch to the reset value in response to a first state of the reset signal.
A configurable latch bank, comprising:
- a pulse generator coupled to receive a clock signal, the pulse generator adapted to pass the clock signal in response to a signal that indicates a clock mode of operation and adapted to generate a variable width pulse signal from the clock signal in response to a signal that indicates a pulse mode of operation;
- and
- a plurality of level sensitive (LS) latches coupled to the pulse generator and adapted to operate as LS latches in response to receiving the clock signal and adapted to operate as edge triggered (ET) latches in response to receiving the variable width pulse signal, the pulse generator including,
- a reset circuit coupled to receive a reset signal and a corresponding reset value for each of the plurality of LS latches, the reset circuit adapted to drive an output of each of the plurality of LS latches to the corresponding reset value in response to a first state of the reset signal.
A configurable latch, comprising:
- a pulse generator coupled to receive a clock input signal and a pulse mode signal, the pulse generator adapted to provide a clock output signal having a programmable duty cycle in response to a logic level of the pulse mode signal;
- and
- a level sensitive (LS) latch coupled to receive the clock output signal, the LS latch adapted to operate as an edge triggered (ET) latch in response to a first duty cycle of the clock output signal and adapted to operate as an LS latch in response to a second duty cycle of the clock output signal,
- wherein the pulse generator comprises a first logic gate coupled to receive the clock input signal at a first input and a clock gating signal at a second input, wherein the first logic gate passes the clock input signal in response to a first level of the clock gating signal and blocks the clock input signal in response to a second level of the clock gating signal, and
- wherein the pulse generator further comprises a second logic gate coupled to receive the pulse mode signal at a first input and coupled to receive the clock output signal at a second input and adapted to provide the second level of the clock gating signal in response to a logic high level of the clock output signal and a logic high level of the pulse mode signal.
Dependencies are inferred from the claim text.