Semiconductor bonding pad structure

A bonding pad structure, comprising:

• a substrate;
• at least one lower circuit layer overlying the substrate, wherein the lower circuit layer is a layout of circuit under pad;
• a top circuit layer overlying the lower circuit layer, wherein the top circuit layer comprises a top interconnect dielectric layer and a top interconnect pattern in the top interconnect dielectric layer;
• a top connecting layer overlying the top circuit layer, electrically connecting the top interconnect pattern;
• and
• a top pad layer overlying the top connecting layer;
• a bonding ball overlying the top pad layer,
• wherein the top interconnect pattern is substantially a hallow pattern, the hallow pattern comprises an inter region, the inter region is within boundary of the bonding ball by about 3 μm, or exceeding boundary of the bonding ball by about 3 μm.

A semiconductor chip, comprising:

• a primary device area at central portion of the semiconductor chip;
• a plurality of bonding pad structures on a periphery area of the chip, wherein each bonding pad structure comprises:
• at least one lower circuit layer, wherein the lower circuit layer is a layout of circuit under pad;
• a top circuit layer overlying the lower circuit layer, wherein the top circuit layer comprises a top interconnect dielectric layer and a top interconnect pattern in the top interconnect dielectric layer;
• a top connecting layer overlying the top circuit layer, electrically connecting the top interconnect pattern;
• a top pad layer overlying the top connecting layer;
• and
• a bonding ball overlying the top pad layer,
• wherein sides of the top interconnect pattern do not overlap a region extending inwardly and outwardly from a boundary of the bonding ball within distance of about 2.5 μm.