High density access transistor having increased channel width and methods of fabricating such devices
AssigneeMicron Technology, Inc.
InventorsHongmei Wang, Chandra Mouli, Luan Tran
Life of this patent
Estimating the term…
Abstract
A memory device having decreased cell size and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The polysilicon layer is patterned to from word lines that intersect the active area lines at the angled segments.
Claims24
A method of fabricating a memory device comprising:
- etching deep trenches in a silicon substrate to form continuous silicon pillars that weave in a direction parallel to the surface of the substrate;
- depositing an isolation material into the deep trenches to completely fill the deep trenches;
- etching shallow trenches in the isolation material such that a portion of the silicon pillars extend from the planar surface of the isolation material;
- forming a gate oxide on a top surface of the silicon pillars and along sidewalls of the silicon pillars;
- and
- depositing a conductive layer, such that the conductive layer fills the shallow trenches and completely covers the gate oxide.
A method of fabricating a memory device comprising:
- etching trenches in a top silicon layer of a silicon on insulator substrate to form continuous silicon pillars that weave in a direction parallel to the surface of the substrate;
- forming a gate oxide on a top surface of the silicon pillars and along sidewalls of the silicon pillars;
- depositing a high-k dielectric material on the gate oxide;
- and
- depositing a conductive layer, such that the conductive layer fills the shallow trenches and completely covers the gate oxide.
A method of fabricating an integrated circuit comprising the acts of:
- forming a plurality of continuous pillars in a substrate material, the pillars extending from the surface of the substrate and forming an array of non-linear rows, wherein each of the non-linear rows are parallel to the surface of the substrate and have a plurality of a plurality of first segments extending in a first direction, a plurality of second segments extending in a second direction and a plurality of third segments extending in a third direction, wherein the first direction and the third direction are complimentary directions and where in the first and third directions are different from that second direction;
- forming a gate oxide along a top surface and sidewalls of the plurality of pillars;
- and
- disposing a conductive layer to completely cover the gate oxide.
Dependencies are inferred from the claim text.