Semiconductor structure with via structure
AssigneeInfineon Technologies AG
InventorsGordon Ma, Carsten Ahrens
Life of this patent
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Abstract
A semiconductor device may comprise a semiconductor substrate having a top and a bottom surface, first and second insulating layer deposited on the top surface of the substrate, a runner arranged on top of the second insulator layer, a backside metal layer deposited on the bottom surface of the substrate, a first via structure extending from the bottom surface of the substrate to the top of the first insulating layer between the backside layer and the runner, and a second via extending from the top of the first insulating layer to the top of the second insulating layer between the first via and the runner.
Claims42
A semiconductor device comprising:
- a semiconductor substrate having a top and a bottom surface,
- first and second insulating layers deposited on the top surface of said substrate,
- a first runner arranged on top of the first insulator layer,
- a second runner arranged on top of the second insulator layer above said first runner,
- a backside metal layer deposited on the bottom surface of the substrate,
- a first via structure extending from the bottom surface of the substrate to the top surface of the substrate between the backside layer and the first runner,
- a second via structure extending from the top surface of the substrate to the top of the first insulating layer between the first via and the first runner,
- a third via structure extending from the top of the first insulating layer to the top of the second insulating layer between the first runner and the second runner, and
- barrier metal layers arranged between the first and second via vias, between the first runner and the second via, between the first runner and the third via, between the third via and the second runner and between the first via and the backside metal layer.
A semiconductor device comprising:
- a semiconductor substrate having a top and a bottom surface,
- first and second insulating layers deposited on the top surface of said substrate,
- a first runner arranged on top of the first insulator layer,
- a second runner arranged on top of the second insulator layer above said first runner,
- a backside metal layer deposited on the bottom surface of the substrate,
- a first via structure extending from the bottom surface of the substrate to the top surface of the substrate between the backside layer and the first runner,
- a second via structure extending from the top surface of the substrate to the top of the first insulating layer between the first via and the first runner, and
- a third via structure extending from the top of the first insulating layer to the top of the second insulating layer between the first runner and the second runner, wherein the first, second and third via structures are arranged within a field effect transistor structure having a source region, a drain region and a gate, in such a way that the first via couples the source region with the backside layer.
Dependencies are inferred from the claim text.