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US 7,253,482 B2Granted
Structure for reducing overlap capacitance in field effect transistors
AssigneeInternational Business Machines Corporation
InventorsHuilong Zhu, Oleg Gluschenkov
Life of this patent
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Abstract
A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations along the width of the gate conductor.
Claims5
A field effect transistor (FET) device, comprising:
- a gate conductor formed over a semiconductor substrate;
- a source region, said source region having a source extension that overlaps and extends under said gate conductor;
- a drain region, said drain region having a drain extension that overlaps and extends under said gate conductor only at selected locations along the width of said gate conductor;
- and
- a liner formed on sidewalls of said gate conductor, wherein said liner is formed at a greater thickness at portions of a drain side of said gate conductor than with respect to remaining portions of said drain side and at a source side of said gate conductor.
2 more elements
A field effect transistor (FET) device, comprising:
- a gate conductor formed over a semiconductor substrate;
- a source region, said source region having a source extension that overlaps and extends under said gate conductor;
- and
- a drain region, said drain region having a drain extension that overlaps and extends under said gate conductor only at selected locations along the width of said gate conductor;
- said drain region further comprising a plurality of recessed areas, said plurality of recessed areas corresponding to areas of said drain region where said extension does not overlap and extend under said gate conductor.
2 more elements
Dependencies are inferred from the claim text.