High performance MOS device with graded silicide
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih-Hao Wang, Ta-Wei Wang, Ching-Wei Tsai
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Abstract
A semiconductor device suffering fewer current crowding effects and a method of forming the same are provided. The semiconductor device includes a substrate, a gate over the substrate, a gate spacer along an edge of the gate and overlying a portion of the substrate, a diffusion region in the substrate wherein the diffusion region comprises a first portion and a second portion between the first portion and the gate spacer. The first portion of the diffusion region has a recessed top surface. The semiconductor device further includes a silicide layer on the diffusion region, and a cap layer over at least the silicide layer. The cap layer provides a strain to the channel region of the semiconductor device.
Claims16
A semiconductor device comprising:
- a substrate;
- a gate over the substrate;
- a spacer liner along an edge of the gate and overlying a portion of the substrate, wherein the spacer liner has a horizontal leg and a vertical leg;
- a gate spacer on the horizontal leg of the spacer liner and comprising a different material from the spacer liner;
- and
- a diffusion region in the substrate with a conductive layer thereon, the conductive layer comprising a first portion, and a second portion having a substantially flat top surface between the first portion and the gate spacer, wherein the first portion has a top surface that is lower than the top surface of the second portion by a step height.
A semiconductor device comprising:
- a substrate;
- a gate over the substrate;
- a spacer liner along an edge of the gate and overlying a portion of the substrate, wherein the spacer liner has a horizontal leg and a vertical leg;
- a gate spacer on the horizontal leg of the spacer liner, wherein the spacer liner and the gate spacer comprise different materials;
- a diffusion region in the substrate with a conductive layer thereon, the conductive layer comprising a first portion and a second portion between the first portion and the gate spacer, wherein the first portion has a top surface that is lower than a top surface of the second portion by a step height, and wherein the second portion has a substantially flat surface;
- and
- wherein the first portion and the second portion of the conductive layer have an interface at a first distance from a respective edge of the gate, and wherein the step height and the first distance have a ratio of between about 1/7 and about 3/7.
A semiconductor device comprising:
- a substrate;
- a gate over the substrate;
- a first gate spacer along an edge of the gate and overlying a portion of the substrate, wherein the first gate spacer comprises a spacer liner having a vertical portion and a horizontal portion, and an additional portion on the horizontal portion of the spacer liner, and wherein the additional portion and the spacer liner comprise different materials;
- a second gate spacer on a sidewall of the first gate spacer, the second gate spacer having a batten, surface in contact with the substrate;
- and
- a source/drain region in the substrate with a conductive layer thereon, the conductive layer comprising a first portion, and a second portion having a substantially flat top surface between the first portion and the second gate spacer, wherein the first portion has a top surface that is lower than the top surface of the second portion by a step height.
Dependencies are inferred from the claim text.