US 7,253,472 B2 · Method of fabricating semiconductor device employing selectivity poly deposition

Abstract

A method for fabricating a semiconductor device employing a selectivity poly deposition is disclosed. The disclosed method comprises depositing selectivity poly on a gate poly and source/drain regions of the silicon substrate, and forming salicide regions on the gate and active regions from the deposited selectivity poly. Accordingly, the present invention employing selectivity poly deposition can reduce or minimize contact surface resistance and improve the electrical characteristics of the semiconductor device by reducing the surface resistance in a miniature semiconductor device. In addition, because the size of the gate electrode is getting small, the present invention can be used as an essential part of the future generations of nano-scale technology. Moreover, mass semiconductor production systems can promptly employ the present invention with existing equipment.

Claims20

Dependent claims

A semiconductor device, comprising:

a) a gate poly structure, comprising a gate poly layer on a gate oxide on a silicon substrate;
b) source/drain regions on the silicon substrate;
c) a selectivity poly on the gate poly layer and the source/drain regions, the selectivity poly on the gate poly layer having a width greater than a gate poly width and the selectivity poly on the source/drain region having a width greater than a corresponding source/drain region width;
and
d) salicide regions on the selectivity poly.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/026,312Filed 28 Dec 2004

Priority

KR 10-2003-010054330 Dec 2003

Published

US 2005/0142825 A130 Jun 2005

Granted

7 Aug 2007

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 30/0212
Of FETs having insulated gates [IGFET]: using self-aligned silicidation
H10D 64/259
Characterised by the relative positions of the source or drain electrodes with respect to the gate electrode: source or drain electrodes being…
H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 84/0174
Manufacturing their gate conductors: the gate conductors being silicided

Method of fabricating semiconductor device employing selectivity poly deposition

Life of this patent

Method of fabricating semiconductor device employing selectivity poly deposition

Life of this patent

Abstract

Claims20