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US 7,253,464 B2Granted
Junction-isolated depletion mode ferroelectric memory devices and systems
AssigneeMicron Technology, Inc.
InventorsCraig T. Salling, Brian W. Huber
Life of this patent
Estimating the term…
Abstract
Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells for memory devices and electronic systems. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb.
Claims21
A memory device, comprising:
- an array of memory cells, wherein each memory cell comprises:
- a ferroelectric layer formed overlying a first well region having a first conductivity type, wherein the first well region is formed overlying a substrate and wherein a layer of dielectric material is interposed between the first well region and the substrate;
- a control gate formed overlying the ferroelectric layer;
- a first source/drain region having the first conductivity type formed in the first well region;
- a second source/drain region having the first conductivity type formed in the first well region;
- a channel region having the first conductivity type formed in the first well region and interposed between the first and second source/drain regions;
- and
- a second well region having the second conductivity type formed in the first well region and coupled to the second source/drain region, wherein the second well region is isolated from the control gate;
- a plurality of word lines coupled to rows of memory cells of the array of memory cells through their control gates;
- a plurality of program lines coupled to columns of memory cells of the array of memory cells through their first source/drain regions;
- a plurality of bit lines coupled to columns of memory cells of the array of memory cells through their second well regions;
- a row decoder coupled to the array of memory cells;
- and
- a column decoder coupled to the array of memory cells.
11 more elements
A memory device, comprising:
- an array of memory cells, wherein each memory cell comprises:
- a ferroelectric layer formed overlying a first well region having a first conductivity type, wherein the first well region is formed overlying a substrate and wherein a layer of dielectric material is interposed between the first well region and the substrate and wherein the ferroelectric layer of each memory cell comprises a material selected from the group consisting of strontium bismuth tantalite, lead zirconium titanate, lanthanum-doped lead zirconium titanate, lithium niobate and metal oxides having a perovskite crystalline structure;
- a control gate formed overlying the ferroelectric layer;
- a first source/drain region having the first conductivity type formed in the first well region;
- a second source/drain region having the first conductivity type formed in the first well region;
- a channel region having the first conductivity type formed in the first well region and interposed between the first and second source/drain regions;
- a gate dielectric layer interposed between the channel region and the ferroelectric layer;
- a conductive floating gate interposed between the gate dielectric layer and the ferroelectric layer;
- and
- a second well region having the second conductivity type formed in the first well region and coupled to the second source/drain region, wherein the second well region is isolated from the control gate;
- a plurality of word lines coupled to rows of memory cells of the array of memory cells through their control gates;
- a plurality of program lines coupled to columns of memory cells of the array of memory cells through their first source/drain regions;
- a plurality of bit lines coupled to columns of memory cells of the array of memory cells through their second well regions;
- a row decoder coupled to the array of memory cells;
- and
- a column decoder coupled to the array of memory cells.
13 more elements
A memory device, comprising:
- an array of memory cells, wherein each memory cell comprises:
- a ferroelectric layer formed overlying a first well region having a first conductivity type, wherein the first well region is formed overlying a substrate and wherein a layer of dielectric material is interposed between the first well region and the substrate and wherein the ferroelectric layer of each memory cell comprises a material selected from the group consisting of strontium bismuth tantalite, lead zirconium titanate, lanthanum-doped lead zirconium titanate, lithium niobate and metal oxides having a perovskite crystalline structure;
- a control gate formed overlying the ferroelectric layer;
- a first source/drain region having the first conductivity type formed in the first well region;
- a second source/drain region having the first conductivity type formed in the first well region;
- a channel region having the first conductivity type formed in the first well region and interposed between the first and second source/drain regions;
- a gate dielectric layer interposed between the channel region and the ferroelectric layer, wherein the ferroelectric layer is overlying and adjoining the gate dielectric layer;
- and
- a second well region having the second conductivity type formed in the first well region and coupled to the second source/drain region, wherein the second well region is isolated from the control gate;
- a plurality of word lines coupled to rows of memory cells of the array of memory cells through their control gates;
- a plurality of program lines coupled to columns of memory cells of the array of memory cells through their first source/drain regions;
- a plurality of bit lines coupled to columns of memory cells of the array of memory cells through their second well regions;
- a row decoder coupled to the array of memory cells;
- and
- a column decoder coupled to the array of memory cells.
12 more elements
A memory device, comprising:
- an array of memory cells, wherein each memory cell comprises:
- a ferroelectric layer formed overlying a first well region having a first conductivity type, wherein the first well region is formed overlying a substrate and wherein a layer of dielectric material is interposed between the first well region and the substrate and wherein the ferroelectric layer of each memory cell comprises a material selected from the group consisting of strontium bismuth tantalite, lead zirconium titanate, lanthanum-doped lead zirconium titanate, lithium niobate and metal oxides having a perovskite crystalline structure;
- a control gate formed overlying the ferroelectric layer;
- a first source/drain region having the first conductivity type formed in the first well region;
- a second source/drain region having the first conductivity type formed in the first well region;
- a channel region having the first conductivity type formed in the first well region and interposed between the first and second source/drain regions, wherein the ferroelectric layer is overlying and adjoining the channel region;
- and
- a second well region having the second conductivity type formed in the first well region and coupled to the second source/drain region, wherein the second well region is isolated from the control gate;
- a plurality of word lines coupled to rows of memory cells of the array of memory cells through their control gates;
- a plurality of program lines coupled to columns of memory cells of the array of memory cells through their first source/drain regions;
- a plurality of bit lines coupled to columns of memory cells of the array of memory cells through their second well regions;
- a row decoder coupled to the array of memory cells;
- and
- a column decoder coupled to the array of memory cells.
11 more elements
An electronic system, comprising:
- a processor;
- and
- a memory device coupled to the processor, wherein the memory device comprises:
- an array of memory cells, wherein each memory cell comprises:
- a ferroelectric layer formed overlying a first well region having a first conductivity type, wherein the first well region is formed overlying a substrate and wherein a layer of dielectric material is interposed between the first well region and the substrate;
- a control gate formed overlying the ferroelectric layer and coupled to a word line;
- a first source/drain region having the first conductivity type formed in the first well region and coupled to a program line;
- a second source/drain region having the first conductivity type formed in the first well region;
- a channel region having the first conductivity type formed in the first well region and interposed between the first and second source/drain regions;
- and
- a second well region having the second conductivity type formed in the first well region and coupled to the second source/drain region, wherein the second well region is isolated from the control gate;
- a plurality of word lines coupled to rows of memory cells of the array of memory cells through their control gates;
- a plurality of program lines coupled to columns of memory cells of the array of memory cells through their first source/drain regions;
- a plurality of bit lines coupled to columns of memory cells of the array of memory cells through their second well regions;
- a row decoder coupled to the array of memory cells;
- and
- a column decoder coupled to the array of memory cells.
14 more elements
Dependencies are inferred from the claim text.