Method of manufacturing thin film transistor
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorHisashi Ohtani
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AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorHisashi Ohtani
Estimating the term…
The object of the present invention is to form a low-concentration impurity region with good accuracy in a top gate type TFT. Phosphorus is added to a semiconductor layer by using a pattern made of a conductive film as a mask to form an N-type impurity region in a self-alignment manner. A positive photoresist is applied to a substrate so as to cover the pattern and then is exposed to light applied to the back of the substrate and then is developed, whereby a photoresist 110 is formed. The pattern is etched by using the photoresist pattern as an etching mask to form a gate electrode. A channel forming region, a source region, a drain region, and low-concentration impurity regions, are formed in the semiconductor layer in a self-alignment manner by using the gate electrode as a doping mask.
An electroluminescence display device comprising:
An organic electroluminescence display device comprising:
An organic electroluminescence display device comprising:
An electroluminescence display device comprising:
An organic electroluminescence display device comprising:
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Dependencies are inferred from the claim text.
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Bodies: characterised by the crystal structures or orientations, e.g. polycrystalline, amorphous or porous
Head-up displays: head mounted
Head mounted: characterised by optical features
Characterised by the gate electrodes: of lateral top-gate TFTs comprising only a single gate
Term ended 20 Jun 2020 (estimated)
1. Field of the Invention
The present invention relates to a method of manufacturing a thin film transistor and an active matrix substrate using the thin film transistor as a switching element.
2. Description of the Related Arts
FIG. 1 is a cross-sectional view showing a manufacturing process of a TFT in accordance with the present invention.
FIG. 2 is a cross-sectional view showing a manufacturing process of a TFT in accordance with the present invention.
FIG. 3 is a cross-sectional view showing a manufacturing process of a CMOS circuit in accordance with the present invention. (Example 1)
The preferred embodiments in accordance with the present invention will be described by using FIG. 1 and FIG. 2.
The present preferred embodiment relates to a manufacturing method of a TFT having an LDD structure. FIG. 1 and FIG. 2 are cross-sectional views showing a manufacturing process and cross-sectional views in the direction of length of the channel of the TFT.
First, an underlayer film 101 is formed on the whole surface of a substrate 100, and an island-shaped semiconductor layer 103 is formed on the underlayer film 101. An insulating film 104 to be a gate insulating film and covering the semiconductor layer 103 is formed on the whole surface of the substrate 100 (see FIG. 1(A)).