Resistance defect assessment device, resistance defect assessment method, and method for manufacturing resistance defect assessment device
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsMichikazu Matsumoto, Yasutoshi Okuno, Katsuyoshi Joukyu, Tetsuya Matsutani
Life of this patent
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Abstract
A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a component of an integrated circuit device, the resistance defect assessment device including test patterns capable of measuring a resistance variation component to be the resistance variation defect in each chip area or each shot area of the wafer, wherein the number of test patterns included in one chip area or one shot area is set so that it is possible to estimate the yield of the integrated circuit device.
Claims21
A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a component of an integrated circuit device, the resistance defect assessment device comprising test patterns capable of measuring a resistance variation component to be the resistance variation defect in each chip area or each shot area of the wafer,
- wherein the number of test patterns included in one chip area or one shot area is set so that it is possible to estimate a yield of the integrated circuit device taking soft-open defects into consideration.
A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a resistive element provided in a semiconductor integrated circuit device, the resistance defect assessment device comprising a resistance defect test pattern having such a length that a resistance variation component to be the resistance variation defect can be measured in each chip area or each shot area of the wafer,
- wherein the number of resistance defect test patterns included in one chip area or one shot area is in a range from B/A×1/100 to B/A×10, where A is the length of the resistance defect test pattern, and B is a total length of the resistive elements provided in the semiconductor integrated circuit device.
A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a resistive element provided in a semiconductor integrated circuit device, the resistance defect assessment device comprising, in each of a plurality of blocks into which each chip area or each shot area of the wafer is divided, a resistance defect test pattern having such a length that a resistance variation component to be the resistance variation defect can be measured and a calibration pattern used for calibrating at least one of a dimension, a thickness and a resistivity of the resistance defect test pattern, which dictate a resistance value of the resistance defect test pattern,
- wherein the blocks are regularly arranged in the wafer surface and in each chip area or each shot area.
A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a resistive element made of a silicon-containing layer and a silicide layer formed on the silicon-containing layer, the resistive element being at least one of a gate electrode wiring and a source/drain impurity layer of a MOS transistor provided in a semiconductor integrated circuit device, the resistance defect assessment device comprising, in each of a plurality of blocks into which each chip area or each shot area of the wafer is divided, a resistance defect test pattern having such a length that a resistance variation component to be the resistance variation defect due to a line break in the silicide layer can be measured and being made of the silicon-containing layer and the silicide layer having the same width as that of the resistive element, and a first calibration pattern having the same length as that of the resistance defect test pattern and being made of the silicon-containing layer having the same width as that of the resistive element,
- wherein the blocks are regularly arranged in the wafer surface and in each chip area or each shot area.
A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a resistive element made of a silicon-containing layer and a silicide layer formed on the silicon-containing layer, the resistive element being at least one of a gate electrode wiring and a source/drain impurity layer of a MOS transistor provided in a semiconductor integrated circuit device, the resistance defect assessment device comprising, in each of a plurality of blocks into which each chip area or each shot area of the wafer is divided, a resistance defect test pattern having such a length that a resistance variation component to be the resistance variation defect due to a line break in the silicide layer can be measured and being made of the silicon-containing layer and the silicide layer having the same width as that of the resistive element, and a second calibration pattern having the same length as that of the resistance defect test pattern and being made of the silicon-containing layer having a width at least five times as large as that of the resistive element,
- wherein the blocks are regularly arranged in the wafer surface and in each chip area or each shot area.
A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a resistive element made of a silicon-containing layer and a silicide layer formed on the silicon-containing layer, the resistive element being at least one of a gate electrode wiring and a source/drain impurity layer of a MOS transistor provided in a semiconductor integrated circuit device, the resistance defect assessment device comprising, in each of a plurality of blocks into which each chip area or each shot area of the wafer is divided, a resistance defect test pattern having such a length that a resistance variation component to be the resistance variation defect due to a line break in the silicide layer can be measured and being made of the silicon-containing layer and the silicide layer having the same width as that of the resistive element, and a third calibration pattern having the same length as that of the resistance defect test pattern and being made of the silicon-containing layer and the silicide layer having a width at least five times as large as that of the resistive element,
- wherein the blocks are regularly arranged in the wafer surface and in each chip area or each shot area.
A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a resistive element made of a silicon-containing layer and a silicide layer formed on the silicon-containing layer, the resistive element being at least one of a gate electrode wiring and a source/drain impurity layer of a MOS transistor provided in a semiconductor integrated circuit device, the resistance defect assessment device comprising, in each of a plurality of blocks into which each chip area or each shot area of the wafer is divided, a resistance defect test pattern having such a length that a resistance variation component to be the resistance variation defect due to a line break in the silicide layer can be measured and being made of the silicon-containing layer and the silicide layer having the same width as that of the resistive element, a first calibration pattern having the same length as that of the resistance defect test pattern and being made of the silicon-containing layer having the same width as that of the resistive element, and a second calibration pattern having the same length as that of the resistance defect test pattern and being made of the silicon-containing layer having a width at least five times as large as that of the resistive element,
- wherein the blocks are regularly arranged in the wafer surface and in each chip area or each shot area.
A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a resistive element made of a silicon-containing layer and a silicide layer formed on the silicon-containing layer, the resistive element being at least one of a gate electrode wiring and a source/drain impurity layer of a MOS transistor provided in a semiconductor integrated circuit device, the resistance defect assessment device comprising, in each of a plurality of blocks into which each chip area or each shot area of the wafer is divided, a resistance defect test pattern having such a length that a resistance variation component to be the resistance variation defect due to a line break in the silicide layer can be measured and being made of the silicon-containing layer and the silicide layer having the same width as that of the resistive element, a first calibration pattern having the same length as that of the resistance defect test pattern and being made of the silicon-containing layer having the same width as that of the resistive element, and a third calibration pattern having the same length as that of the resistance defect test pattern and being made of the silicon-containing layer and the silicide layer having a width at least five times as large as that of the resistive element,
- wherein the blocks are regularly arranged in the wafer surface and in each chip area or each shot area.
A contact defect assessment device provided on a wafer for assessing a resistance variation defect in a contact provided in a semiconductor integrated circuit device, the contact defect assessment device comprising a contact chain resistor pattern having such a number of contacts that a resistance variation component to be the resistance variation defect can be measured in each chip area or each shot area of the wafer,
- wherein the number of contact chain resistor patterns included in one chip area or one shot area is in a range from N/n×1/10 to N/n×10, where n is the number of contacts in one contact chain resistor pattern, and N is the total number of contacts provided in the semiconductor integrated circuit device.
Dependencies are inferred from the claim text.