Controllable ovonic phase-change semiconductor memory device

An integrated circuit device comprising:

• a first electrode having a first portion and a second portion, a width of the first electrode narrowing substantially and continuously in a direction extending from the second portion toward the first portion of the first electrode;
• an insulative layer proximate the first electrode;
• a layer of programmable resistive material in contact with the first portion of the first electrode and overlying directly above at least part of the insulative layer, the programmable resistive material capable of being reversibly cycled;
• and
• a second electrode coupled to the layer of programmable resistive material.

A semiconductor memory cell comprising:

• a first conductive layer on a substrate, wherein the first conductive layer includes at least one raised portion;
• an insulative layer proximate the at least one raised portion;
• a programmable resistive material in direct contact with the at least one raised portion of the first conductive layer and overlying directly above at least part of the insulative layer, the programmable resistive material configured to switch between different resistive states;
• and
• a second conductive layer above the programmable resistive material.