Process for defect reduction in electrochemical plating

#The invention is generally related to the field of fabricating copper interconnects in semiconductor devices and more specifically to a defect reduction in electrochemical copper plating.

#As the density of semiconductor devices increases, the demands on interconnect layers for connecting the semiconductor devices to each other also increases. Therefore, there is a desire to switch from the traditional aluminum metal interconnects to copper interconnects. Unfortunately, suitable copper etches for a semiconductor fabrication environment are not readily available. To overcome the copper etch problem, damascene processes have been developed.

#In a conventional interconnect process, the aluminum (and any barrier metals) are deposited, patterned, and etched to form the interconnect lines. Then, an interlevel dielectric (ILD) is deposited and planarized. In a damascene process, the ILD is formed first. The ILD is then patterned and etched. The barrier material is then deposited over the structure with the copper being formed over the barrier material. Then, the copper and barrier material are chemically-mechanically polished to remove the conducting material from over the ILD, leaving metal interconnect lines. A metal etch is thereby avoided.

#In the drawings:

#FIGS. 1A-1C are cross-sectional drawings of a copper interconnect structure formed according to the invention; and

#FIG. 2 is a graph of defect counts at post-metal-3 ECD and CMP.

#The invention will now be discussed in conjunction with a via-first dual damascene copper interconnect process. It will be apparent to those of ordinary skill in the art that the benefits of the invention apply generally to ECD of copper in the semiconductor fabrication environment.

#Embodiments of the invention will now be discussed with reference to FIGS. 1A-1C. A semiconductor body 100 is processed through formation of the seed layer 112. Semiconductor body 100 typically comprises a silicon substrate having transistors and other elements formed therein. Seed layer 112 is part of a copper interconnect level 114. Copper interconnect level 114 may be the first or any subsequent metal interconnect level of the semiconductor device 120.

#An ILD 102 is formed over semiconductor body 100. IMD (intrametal dielectric) 104 is formed over ILD 102. An etchetop layer (not shown) may optionally be placed between ILD 102 and IMD 104. Suitable dielectrics for ILD 102 and IMD 104, such as silicon dioxides, fluorine-doped silicate glass (FSG), organo-silicate glass (OSG), hydrogen silesquioxane (HSQ), and combinations thereof, are known in the art.