Dual damascene etch processes

#The present application relates to semiconductor processing technologies, and particularly to etching patterns in a layer of dielectric material having low dielectric constant.

#The performance, density, and cost of integrated circuit (IC) chips have been improving at a dramatic rate. Much of the improvement has been due to the ability to scale transistors to increasingly smaller dimensions, resulting in higher speed and higher functional density. The continued shrinking of transistor sizes on the IC chips, however, poses many challenges to back-end interconnects. As the minimum feature size on the IC's shrinks below 0.18 μm, the metal interconnect lines become thinner and more densely packed, resulting in greater resistance in the metal lines and larger inter-metal capacitance, and therefore a longer time delay or slower operating speed. By changing to different materials, i.e., higher conductivity material for the metal lines and lower permittivity (low-k) dielectric for the insulating material, device geometry can continue to shrink without adversely impacting the maximum operating speed. This prompted the switch from aluminum and silicon dioxide to copper and low-k dielectrics in the backend process flow for manufacturing many current and future IC devices.

#The switch from aluminum/oxide to copper/low-k involves a variety of fundamental changes in the backend manufacturing process flow. Since it is difficult to etch copper, new approaches such as “damascene” or “dual damascene” processing are required. Copper damascene/dual-damascene is a process where VIAs and/or trenches are etched into the insulating material. Copper is then filled into the VIAs and/or trenches and sanded back using a process such as chemical mechanical polishing (CMP), so the conducting materials are only left in the VIAs and trenches. In the dual damascene approach, both VIAs and trenches are patterned into a layer of dielectric material or a stack of different dielectric materials before copper fill. An advantage of this approach is that only one copper fill and CMP is necessary to form a layer of metal lines and VIAs that connect the layer of metal lines to another layer of metal lines. The dual damascene approach, however, may require a rather complex dielectric stack that includes a sequence of hard mask, low-k dielectrics, and etch stop layers.

#Additional objects and features of the invention will be more readily apparent from the following detailed description and appended claims when taken in conjunction with the drawings, in which:

#FIGS. 1A to 1E are schematic views in vertical cross-section of a dielectric stack at different stages in a conventional VIA-first dual damascene etching sequence;

#FIG. 2A is a schematic view in vertical cross-section of a dielectric stack after BARC fill and before trench etching;

#The present invention includes an etching process for etching dual damascene trenches after VIAs are formed in a dielectric stack. FIG. 3 illustrates in vertical cross-section section a group of VIAs, such as VIAs 301, 302, and 303, in a dielectric stack, according to one embodiment of the present invention. The dielectric stack includes a hard mask layer 320 over a low-k dielectric layer 330 formed on a substrate 360. Metal lines 350 lie under portions of the low-k dielectric layer 330 and are separated from the low-k dielectric layer 330 by a barrier/liner layer 340. A BARC material 315 is spin-applied to fill the VIAs 301, 302, and 303 and cover the hard mask layer 320. A trench mask 310 is formed over the BARC 315 to define trench openings, such as trench opening 305 on top of VIA 302. As is shown, because isolated VIAs, such as VIA 302, are filled more easily by the BARC 315 than VIAs in dense VIA areas, such as VIAs 301 and 303, the BARC 315 on top of the hard mask layer 120 over dense VIAs is thinner than that over isolated VIAs.

#The etching process of the present invention can be performed in a plasma reactor, such as, for example, the Dielectric Etch eMAX system, the Dielectric Etch Super e Centura system, or the Dielectric Etch IPS Centura system, all of which are commercially available from Applied Materials Inc., Santa Clara, Calif. FIG. 4 illustrates a magnetically enhanced reactive ion etching (MERIE) reactor 200, as one example of a reactor that can be used to carry out the etching process in one embodiment of the present invention. The reactor 200 comprises a chamber 210 enclosed by a wall 212, a base 214, and a ceiling 260. The chamber includes a process zone 201 comprising a volume of about 5,000 to about 50,000 cm3. The reactor 200 further comprises a process gas supply 220 that supplies gases into the chamber 210 through a gas manifold 262 and a gas distribution plate (GDP) 264 at the ceiling 260 of the chamber 210. Spent process gas and volatile etch products are pumped out from the process chamber 210 by a pump 240. A throttle valve 245 controls the pressure in the chamber 210. The wall 212, the base 214, the ceiling 260, and the GDP 264 are usually made of aluminum with anodized aluminum coating on at least the surfaces facing the inside of the chamber 210. The wall 212, the base 214, the ceiling 260, and the GDP 264 are typically grounded. The chamber 210 further includes a pedestal 230 that supports a substrate, such as substrate 360, in the chamber 210. The pedestal 230 is electrically isolated from the base 214 by an insulator support ring 232 and is connected to a radio frequency (RF) power source 250 through an impedance match network 255.

#A controller 280 comprising a CPU 282, a memory 284, and support circuits 286 for the CPU 282 is coupled to the various components of the reactor 200 to facilitate control of the various components of the reactor 200. The memory 284 can be any computer-readable medium, such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote to the reactor 200 or CPU 282. A software routine or a series of program instructions stored in the memory 284, when executed by the CPU 282, causes the reactor 200 to perform processes of the present invention.