Self-aligned method for defining a semiconductor gate oxide in high voltage device area

A method for forming a semiconductor device comprising:

• providing a substrate with designated high voltage (HV) and low voltage (LV) areas;
• forming a plurality of gate oxides including at least one thick gate oxide in said HV area and at least one thin gate oxide in said LV area, each thick gate oxide being thicker than each thin gate oxide;
• forming a pattern of poly features in each of said high voltage and low voltage areas, said poly features including polysilicon covered by a hardmask;
• plasma etching to remove said at least one thick gate oxide from said HV area that is not masked by a hardmask;
• and
• wet etching to remove said at least one thin gate oxide from said LV area not masked by one of said poly features.

A method for forming a semiconductor device comprising:

• providing a substrate with designated high voltage (HV) and low voltage (LV) areas;
• forming a plurality of gate oxides including at least one thick gate oxide in said HV area and at least one thin gate oxide in said LV area, each thick gate oxide being thicker than each thin gate oxide;
• forming masking patterns over said plurality of gate oxides, said masking patterns including patterned photoresist sections and poly features including polysilicon covered by a hardmask;
• plasma etching using a selective oxide etch that removes portions of said plurality of gate oxides not covered by said masking patterns;
• removing said patterned photoresist sections;
• and
• wet etching to remove portions of said at least one thin gate oxide from areas not masked by one of said poly features.