Method of manufacturing semiconductor device that includes forming self-aligned contact pad

A method comprising:

• preparing a semiconductor substrate on which an active region and a device isolation region are defined;
• forming a gate electrode stack including a gate oxide film, a gate conductive film, and a hard mask on the semiconductor substrate;
• forming a spacer on a sidewall of the gate electrode stack, thereby forming a gate electrode structure comprising the gate electrode stack and the spacer;
• forming a source region and a drain region in the semiconductor substrate;
• forming a first interlayer insulating layer on the semiconductor substrate, the first interlayer insulating layer having a thickness greater than that of the gate electrode structure;
• forming an etch inducing and focusing mask on the first interlayer insulating layer, the etch inducing and focusing mask extending in a length direction of the gate electrode structure and covering the gate electrode stack;
• forming a second interlayer insulating layer on the first interlayer insulating layer, the second interlayer insulating layer having a thickness that is equal to or greater than a thickness of the etch inducing and focusing mask;
• forming a photoresist pattern on the second interlayer insulating layer;
• sequentially etching the second interlayer insulating layer and the first interlayer insulating layer using the photoresist pattern as an etch mask to form a SAC hole exposing a portion of the gate electrode structure and a portion of the semiconductor substrate adjacent to the gate electrode structure, wherein the first interlayer insulating layer and the second interlayer insulating layer are selectively etched with respect to the etch inducing and focusing mask;
• and
• filling a conductive material in the SAC hole to form a SAC pad.

A method comprising:

• forming a conductive line structure on a semiconductor substrate;
• forming a first interlayer insulating layer on the semiconductor substrate, the first interlayer insulating layer having a thickness greater than that of the conductive line structure;
• forming an etch inducing and focusing mask on the first interlayer insulating layer, the etch inducing and focusing mask extending in the same direction as a length direction of the conductive line structure and covering the conductive line structure;
• forming a second interlayer insulating layer on the first interlayer insulating layer, the second interlayer insulating layer having a thickness that is equal to or greater than a thickness of the etch inducing and focusing mask;
• forming a photoresist pattern on the second interlayer insulating layer;
• etching the second interlayer insulating layer and the first interlayer insulating layer using the photoresist pattern as an etch mask to form a SAC hole exposing a shoulder of the conductive line structure and a portion of the semiconductor substrate adjacent to the conductive line structure, wherein the first interlayer insulating layer is selectively etched with respect to the etch inducing and focusing mask;
• and
• filling a conductive material in the SAC hole to form a SAC pad.