Integrated circuit system using dual damascene process

A method comprising:

• providing a semiconductor substrate having a semiconductor device provided thereon;
• forming a first dielectric layer over the semiconductor substrate;
• forming a first conductor core in the first dielectric layer;
• forming a stop layer over the first conductor core;
• forming a second dielectric layer over the stop layer;
• forming a channel and a via in the second dielectric layer and the via closed to the first conductor core;
• wet cleaning the channel and the via in the second dielectric layer while the stop layer is present;
• depositing a barrier metal layer to line the channel and the via in the second dielectric layer;
• selectively etching the barrier metal layer and the stop layer from the bottom of the via in the dielectric layer only after wet cleaning the channel and the via;
• then forming a second conductor core over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.

A method for reducing contaminants in a via connecting a first and a second conductor cores in an integrated circuit, comprising:

• forming a stop layer over the first conductor core;
• forming a dielectric layer over the stop layer;
• forming the via in the dielectric layer and in the stop layer closed to the first conductor core;
• wet cleaning the via in the presence of the stop layer;
• depositing a barrier metal layer to line the via;
• selectively etching the barrier metal layer and the stop layer from the bottom of the via in the dielectric layer after wet cleaning the via;
• then forming a second conductor core over the barrier metal layer to fill the via to connect the second conductor core to the first conductor core.