US 7,253,088 B2 · Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same

Abstract

A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.

Claims12

Dependent claims

A process comprising:

mating a microelectronic die substrate to a board, wherein the substrate includes an upper surface, a lower surface, and a solder first bump disposed on the lower surface, wherein the solder first bump is selected from:
36%≦indium≦63%;
28%≦tin≦48%;
and 2%≦bismuth 26%;
42%≦bismuth≦62%;
19%≦tin≦42%;
and 7%≦indium 28%;
33%≦indium≦67%;
32%≦bismuth≦67%;
and 0.1%≦tin≦20%;
52%≦indium≦54% indium;
0.01%≦zinc≦2%;
and 46%≦tin≦48%;
or
33%≦indium≦67%;
32%≦bismuth≦67%;
and 0.1%≦zinc≦1%;
and
forming a stress-compensation collar (SCC) on the board during mating the die and the board, wherein the SCC abuts the solder first bump.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application

10/954,999Filed 29 Sep 2004

Published

US 2006/0068579 A130 Mar 2006

Granted

7 Aug 2007

Term ends

Not estimatedThe source records don’t support an estimate.

Classification17 codes

H05K 3/3436
Leadless components: having an array of bottom contacts, e.g. pad grid array or ball grid array components
H05K 3/346
By soldering: solder materials or compositions specially adapted therefor
H10W 42/121
Arrangements for protection of devices: protecting against mechanical damage
H05K 1/0271
Details: arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal…

Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same

Life of this patent

Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same

Life of this patent

Abstract

Claims12