Cascode I/O driver with improved ESD operation
AssigneeMicron Technology, Inc.
InventorsMichael D. Chaine, Manny K. F. Ma
Life of this patent
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Abstract
A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An system is described that includes an I/O driver in parallel with an ESD device. In an embodiment, the I/O driver may assist the ESD device in discharging electrostatic, after the ESD begins conducting.
Claims38
A method, comprising:
- forming a first transistor in a substrate;
- forming a second transistor in the substrate having a shared source/drain region with the first transistor;
- forming a barrier in the shared region;
- and
- forming a non-conducting region between a drain region of the first transistor and a source region of the second transistor in a portion of a doped well, wherein the width of the non-conductive region is adjusted to provide a specified breakdown voltage of a parasitic feature.
A method, comprising:
- simultaneously forming a first transistor and a second transistor in a substrate such that the first and second transistors are in a cascode configuration with a shared region;
- forming a barrier in the shared region;
- and
- forming a non-conducting region between the first transistor and the second transistor in a portion of a doped well, wherein the width of the non-conductive region is adjusted to provide a specified breakdown voltage of a parasitic bipolar transistor.
A method, comprising:
- forming a doped region having a first conductivity type in a substrate;
- forming a set of cascode-connected transistors having channels in the doped region;
- forming a barrier in a shared region of the cascode-connected transistors;
- and
- forming a non-conducting region between the set of cascode-connected transistors in a portion of a doped well, wherein the width of the non-conductive region is to provide a specified breakdown voltage of a parasitic feature.
A method, comprising:
- forming a doped region having a first conductivity type in a substrate;
- forming a set of cascode-connected transistors having channels in the doped region, wherein forming the set of transistors includes:
- forming a first diffusion region having a second conductivity type in the doped region;
- forming a second diffusion region having the second conductivity type in the doped region;
- and
- forming a third diffusion region having the second conductivity type in the doped region;
- forming a barrier in the second diffusion region;
- and
- forming a non-conducting region between the set of cascode-connected transistors in a portion of a doped well, wherein forming the non-conducting region includes adjusting the width of the non-conductive region to provide a specified parasitic breakdown voltage.
A method, comprising:
- forming a doped region having a first conductivity type in a substrate;
- forming a set of cascode-connected transistors having channels in the doped region, wherein forming the set of transistors includes:
- forming a first diffusion region in the doped region;
- forming a second diffusion region in the doped region;
- and
- forming a third diffusion region in the doped region;
- and
- forming a barrier in the second diffusion region such that the barrier extends through the second diffusion region into the doped region, wherein forming a barrier includes forming the barrier with at least one of a width and a depth of the barrier being adjusted to provide a specified parasitic breakdown voltage.
A method for improving operation of a cascode-type driver in an output buffer of an integrated circuit, comprising:
- inserting a gap in the common node of the cascode-connected transistors, wherein a width of the gap is used to adjust a breakdown voltage of a parasitic transistor.
Dependencies are inferred from the claim text.