Method for forming a storage cell capacitor compatible with high dielectric constant materials

A method for fabricating an integrated circuit capacitor, comprising:

• forming an electrically insulative layer overlying a substrate;
• forming an opening in said insulative layer in order to expose said substrate;
• forming a conductive plug in said opening, said conductive plug forming a first portion of a first electrode of said capacitor, wherein the conductive plug includes polysilicon;
• providing a recess in said opening between a surface of said insulative layer and a surface of said conductive plug;
• forming a diffusion barrier layer in said recess such that a sidewall of said diffusion barrier layer is surrounded by said insulative layer, said diffusion barrier layer overlying said conductive plug and forming a second portion of said first electrode;
• forming a conductive oxidation resistant layer overlying said insulative layer and in the recess overlying said diffusion barrier layer, said diffusion barrier layer configured to inhibit diffusion of atoms between said conductive plug and said conductive oxidation resistant layer;
• removing portions of the conductive oxidation resistant layer overlying said insulative layer while retaining portions of said conductive oxidation resistant layer in the recess, remaining portions of the conductive oxidation resistant layer forming a third portion of said first electrode;
• removing portions of said insulative layer to expose an upper portion of a sidewall of said conductive oxidation resistant layer;
• retaining a portion of said insulative layer at a lower portion of said sidewall of said conductive oxidation resistant layer;
• forming a dielectric layer overlying said conductive oxidation resistant layer;
• forming a second electrode overlying said dielectric layer, said first and said second electrodes and said dielectric layer forming the capacitor;
• and
• forming a reducing contact resistance layer interposed between said conductive plug and said diffusion barrier layer, said reducing contact resistance layer configured to reduce a contact resistance between said conductive plug and said diffusion barrier layer, wherein the reducing contact resistance layer includes silicide.

A method for fabricating an electrode, comprising:

• forming an electrically insulative layer overlying a substrate;
• masking the insulative layer to define a future opening in the insulative layer;
• etching the insulative layer in an exposed region to form the opening and to expose the substrate;
• forming a contact to the substrate in the opening, wherein the contact includes polysilicon;
• recessing a top surface of the contact from a surface of the insulative layer;
• forming a diffusion barrier layer overlying the contact;
• removing portions of the diffusion barrier layer overlying the insulative layer;
• forming a conductive oxidation resistant layer overlying the diffusion barrier layer;
• removing portions of the conductive oxidation resistant layer overlying the insulative layer;
• removing upper portions of the insulative layer to expose an upper sidewall of the conductive oxidation resistant layer, wherein said conductive oxidation resistant layer, said diffusion barrier layer, and said contact form the electrode;
• and
• forming a reducing contact resistance layer interposed between said contact and said diffusion barrier layer, said reducing contact resistance layer configured to reduce a contact resistance between said contact and said diffusion barrier layer, wherein the reducing contact resistance layer includes silicide.