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US 7,253,049 B2Granted
Method for fabricating dual work function metal gates
AssigneeTexas Instruments Incorporated
InventorsJiong-Ping Lu, Shaofeng Yu, Haowen Bu, Lindsey H. Hall, Mark R. Visokay
Life of this patent
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Abstract
A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate 20 that includes having a gate protection layer 210 over the gate electrode layer 110 during the formation of source/drain silicides 120. The method may include implanting dopants into a gate polysilicon layer 115 before forming the protection layer 215.
Claims30
A method for making PMOS and NMOS transistors on a semiconductor wafer, comprising:
- providing a semiconductor substrate;
- forming a gate oxide layer over said semiconductor substrate;
- forming a gate polysilicon layer over said gate oxide layer;
- implanting dopants into said gate polysilicon layer;
- forming a protection layer over said gate polysilicon layer
- etching said protection layer, said gate polysilicon layer, and said gate oxide layer to form gate stacks having a gate protection layer, a gate electrode, and a gate dielectric;
- implanting extension regions within a top surface of said semiconductor substrate;
- forming spacer sidewalls coupled to said extension sidewalls;
- implanting source/drain regions within a top surface of said semiconductor substrate;
- annealing said semiconductor wafer to create sources/drains;
- forming a first layer of silicidation metal over said semiconductor wafer;
- performing a silicide anneal to create a silicide within a top surface of said sources/drains;
- and
- removing said gate protection layer of said gate stacks.
11 more elements
A method for making PMOS and NMOS transistors on a semiconductor wafer, comprising:
- providing a semiconductor substrate;
- forming a gate oxide layer over said semiconductor substrate;
- forming a gate polysilicon layer over said gate oxide layer;
- and
- forming a protection layer over said gate polysilicon layer, said protection layer having a top and bottom layer of silicon nitride coupled to a middle layer of silicon oxide;
- etching said protection layer, said gate polysilicon layer, and said gate oxide layer to form gate stacks having a gate protection layer, a gate electrode, and a gate dielectric;
- forming extension sidewalls coupled to said gate stacks;
- implanting extension regions within a top surface of said semiconductor substrate;
- forming spacer sidewalls coupled to said extension sidewalls;
- removing said top layer of silicon nitride and said middle layer of silicon oxide of said gate protection layer;
- implanting source/drain regions within a top surface of said semiconductor substrate;
- annealing said semiconductor wafer to create sources/drains;
- forming a first layer of silicidation metal over said semiconductor wafer;
- performing a self-aligned silicide anneal process to create a silicide within a top surface of said sources/drains;
- removing said bottom layer of silicon nitride of said gate protection layer;
- forming a second layer of silicidation metal over said semiconductor wafer;
- and
- performing a gate silicide anneal to create a gate silicide within a top surface of said gate electrode.
15 more elements
Dependencies are inferred from the claim text.