Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry
AssigneeMicron Technology, Inc.
InventorLuan C. Tran
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Abstract
Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of the active areas having different widths. A gate line is formed over the active areas to provide transistors having different threshold voltages. In one embodiment, the transistors are provided with different threshold voltages without using a separate channel implant for the transistors.
Claims45
A semiconductor processing method of forming transistors comprising:
- forming a plurality of shallow trench isolation regions received within a substrate, the shallow trench isolation regions being formed to define a plurality of active areas having widths within the substrate, some of the widths being no greater than about one micron, at least two of the widths being different;
- forming a gate line over respective active areas to provide individual transistors, the transistors corresponding to the active areas having the different widths having different threshold voltages, wherein a transistor corresponding to an active area having a smaller of the different widths has a lower of the different threshold voltages;
- and
- wherein the active areas having the different widths each comprise a width of less than one micron.
A semiconductor processing method of forming transistors comprising:
- forming a plurality of shallow trench isolation regions received within a substrate, the shallow trench isolation regions being formed to define a plurality of active areas having widths over the substrate, at least two of the widths being different, at least one of the plurality of active areas having a width less than one micron;
- forming a gate line over respective active areas to provide individual transistors having different threshold voltages, the transistors being provided with the different threshold voltages without using separate channel implants for different ones of the transistors;
- performing a plurality of channel implants common to the transistors to provide the different threshold voltages;
- and
- wherein a transistor with a lower one of the threshold voltages corresponds to the active area having a smaller one of the widths.
A semiconductor processing method of forming transistors comprising:
- forming a plurality of shallow trench isolation regions received within a substrate, the shallow trench isolation regions being formed to define a plurality of active areas having widths within the substrate, some of the widths being no greater than about one micron, at least two of the widths being different;
- and
- forming a gate line over respective active areas to provide individual transistors, the transistors corresponding to the active areas having the different widths having different threshold voltages without using a separate channel implant for the transistors, wherein the different threshold voltages are each less than 2 volts.
A semiconductor processing method of forming transistors comprising:
- forming a plurality of shallow trench isolation regions received within a substrate, the shallow trench isolation regions being formed to define a plurality of active areas having widths over the substrate, at least two of the widths being different, at least one of the plurality of active areas having a width less than one micron;
- forming a gate line over respective active areas to provide individual transistors having different threshold voltages, the transistors being provided with the different threshold voltages without using separate channel implants, wherein forming the gate line comprises forming a common gate line over the plurality of active areas, the transistors being formed in an electrically parallel configuration;
- and
- wherein a transistor with a lower one of the threshold voltages corresponds to the active area having a smaller one of the widths.
Dependencies are inferred from the claim text.