US 7,253,046 B2 · Semiconductor memory device and manufacturing method thereof

Abstract

After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is formed in a memory cell array region (11) by an ion implantation as a resist pattern (16) taken as a mask, then lattice defects are given to the silicon nitride film (22) by a further ion implantation. Accordingly, a highly reliable semiconductor memory device can be realized, in which a high quality nitride film is formed in a low temperature condition, in addition, the nitride film can be used as a charge trap film having a charge capture function sufficiently adaptable for a miniaturization and a high integration which are recent demands.

Claims17

Dependent claims

A manufacturing method of a semiconductor memory device, comprising the steps of:

forming an insulating film including a nitride film formed on a semiconductor substrate by nothing but a plasma nitriding method or by a series of processes including the plasma nitriding method;
forming a pair of impurity diffusion layers with an impurity introduced into a surface layer of the semiconductor substrate;
forming charge trap centers with lattice defects given to portions corresponding to at least on the impurity diffusion layers of the nitride film before or after the formation of the impurity diffusion layer;
and
forming a gate electrode so as to cross the impurity diffusion layer through the insulating film.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/065,305Filed 25 Feb 2005 · continuation

Priority

JP 2002-25552830 Aug 2002

Published

US 2005/0224866 A113 Oct 2005

Granted

7 Aug 2007

Term ends

Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10P 14/69433
Containing silicon: the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
H10B 43/30
EEPROM devices comprising charge-trapping gate insulators: characterised by the memory core region
H10B 43/40
EEPROM devices comprising charge-trapping gate insulators: characterised by the peripheral circuit region
H10D 30/0413
Of FETs having insulated gates [IGFET]: of FETs having charge-trapping gate insulators, e.g. MNOS transistors

Semiconductor memory device and manufacturing method thereof

Life of this patent

Semiconductor memory device and manufacturing method thereof

Life of this patent

Abstract

Claims17