Method of fabricating thin film transistor
AssigneeSamsung SDI Co., Ltd.
InventorIn-Young Jung
Life of this patent
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Abstract
A method of fabricating a thin film transistor is provided. The method comprises first preparing a substrate and forming an amorphous silicon layer on the substrate. A catalyst construction is then positioned on the amorphous silicon layer and an anode and a cathode are then connected to the catalyst construction. A predetermined amount of electric power is then delivered to the anode and the cathode, generating joule heat which then crystallizes the portion of the amorphous silicon layer on which the catalyst construction is positioned, thereby forming a polysilicon layer. The remaining portion of the amorphous silicon layer is then crystallized to a polysilicon layer by propagating the crystallization of the portions of the polysilicon layer on which the catalyst construction is positioned.
Claims19
A method of fabricating a thin film transistor comprising:
- preparing an insulative substrate;
- forming an amorphous silicon layer on the insulative substrate;
- forming a catalyst construction on at least a portion of the amorphous silicon layer;
- connecting at least one anode and at least one cathode to the catalyst construction;
- delivering a predetermined amount of electric power to the anode and the cathode, wherein the delivered electric power generates joule heat in the catalyst construction, and wherein the generated joule heat heats the amorphous silicon layer to a temperature rangina from about 800 to about 1,000° C.;
- crystallizing the portion of the amorphous silicon layer on which the catalyst construction is positioned using the generated joule heat;
- and
- crystallizing a remaining portion of the amorphous silicon layer by propagating the crystallization of the portion of the amorphous silicon layer on which the catalyst construction is positioned, thereby forming a crystallized polysilicon layer.
A method of fabricating a thin film transistor comprising:
- preparing an insulative substrate;
- forming an amorphous silicon layer on the insulative substrate;
- forming a catalyst construction on at least a portion of the amorphous silicon layer;
- connecting at least one anode and at least one cathode to the catalyst construction;
- delivering a predetermined amount of electric power to the anode and the cathode, wherein the delivered electric power generates joule heat in the catalyst construction ,and wherein the generated joule heat heats the amorphous silicon layer to a temperature ranging from about 800 to about 1,000° C.;
- crystallizing the portion of the amorphous silicon layer on which the catalyst construction is positioned using the generated joule heat;
- crystallizing a remaining portion of the amorphous silicon layer by propagating the crystallization of the portion of the amorphous silicon layer on which the catalyst construction is
- positioned, thereby forming a crystallized polysilicon layer;
- positioning a gate insulating layer over an entire surface of the substrate;
- positioning a gate electrode on the gate insulating layer;
- positioning an interlayer insulating layer on the entire surface of the substrate;
- etching the interlayer insulating layer and the gate insulating layer to form openings;
- depositing a source/drain electrode layer on the entire surface of the substrate;
- and
- patterning the source/drain electrode layer to form source/drain electrodes.
Dependencies are inferred from the claim text.