Method of fabricating high-voltage CMOS device
AssigneeDongbu Electronics Co., Ltd.
InventorKwang Young Ko
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Abstract
The present invention provides a method of fabricating a high-voltage CMOS device, in which an extended drain region failing to enclose a heavily-doped drain region is separated from a high current flow path to enable high electric field concentration and breakdown to occur within a bulk of a silicon substrate and by which device reliability can be enhanced. The present invention includes the steps of forming a pad oxide layer on a substrate, forming a heavily doped drain region, a heavily doped source region, a source region, and an extended drain region failing to enclose the heavily doped drain region by ion implantation using a pattern provided on the pad oxide layer, forming a field oxide layer on a prescribed area of the extended drain region, and forming a gate and a gate spacer over the substrate.
Claims3
A method of fabricating a high-voltage CMOS device, comprising the steps of:
- forming a pad oxide layer on a substrate;
- forming an extended drain region by ion implantation using a first pattern provided on the pad oxide layer;
- forming a heavily doped drain region and a heavily doped source region by ion implantation using a second pattern provided on the pad oxide layer, wherein the heavily doped drain region is not enclosed by the extended drain region;
- forming a source region by ion implantation using a third pattern provided on the pad oxide layer;
- forming a field oxide layer on a prescribed area of the extended drain region using a fourth pattern provided on the substrate;
- and
- forming a gate and a gate spacer over the substrate after forming the field oxide layer,
- wherein the extended drain region is formed between the heavily doped drain region and the substrate.
Dependencies are inferred from the claim text.