Print head driving circuit

A driving circuit for a print head having a plurality of nozzles, said print head driving circuit comprising:

• a current amplifying section for outputting a drive signal of an amplified current to a plurality of nozzle driving sections for driving said respective nozzles;
• and
• a voltage signal generating section which generates a voltage signal for controlling driving of the current amplifying section, converts digital data, which is a parameter for determining a waveform of a voltage signal, to analog data, generates a voltage signal on the basis of the analog data, and outputs the voltage signal to the current amplifying section,
• said current amplifying section comprising:
• a first stage current amplifying element that operates in accordance with a voltage signal input thereto;
• a second stage current amplifying element that changes said drive signal output to said respective nozzle driving sections, in accordance with an output signal from said first stage current amplifying element;
• and
• an input potential restricting section, driven when the input potential to said second stage current amplifying element exceeds a prescribed value, for shorting out the input side of said second stage current amplifying element until the input potential falls to or below a prescribed value,
• the second-stage current amplifying element comprising:
• an NPN-type transistor which constitutes a drive voltage transmission path that connects the current amplifying section with the respective nozzle driving sections, and a charging circuit for piezo elements included in the respective nozzle driving sections;
• and
• a PNP-type transistor which is connected in a push-pull configuration to the NPN-type transistor, and which constitutes the drive voltage transmission path and a discharging circuit for the respective piezo elements,
• the first-stage current amplifying element comprising:
• an NPN-type transistor which is connected in a Darlington configuration to the second-stage NPN-type transistor;
• and
• a PNP-type transistor which is connected in a Darlington configuration to the second-stage NPN-type transistor, and which is connected in a push-pull configuration to the first-stage NPN-type transistor,
• an emitter terminal of the first-stage NPN-type transistor being directly connected to an emitter terminal of the first-stage PNP-type transistor and a base terminal of the second-stage NPN-type transistor, and
• the voltage signal being output to the base terminal of the first-stage NPN-type transistor and the base terminal of the first-stage PNP-type transistor.