Optimized translation of scalar type SIMD instructions into non-scalar SIMD instructions
AssigneeIntel Corporation
InventorsYun Wang, Orna Etzion
Life of this patent
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Abstract
An arrangement is provided for translating a plurality of scalar single instruction multiple data stream (SIMD) instructions into a plurality of optimized non-scalar SIMD instructions to be executed on a target architecture supporting only parallel SIMID instructions. After receiving a plurality of scalar SIiVLD instructions, translation from the scalar SIMD instructions to non-scalar SIMD instructions is performed. The translation is optimized so that the number of translated non-scalar SIMD instructions is minimized. The translated non-scalar SIIViD instructions are executed on a target architecture that supports only parallel SIMD instructions.
Claims26
A method comprising:
- receiving, at a translator of a processing system, a plurality of scalar single instruction multiple data stream (SIMD) instructions;
- identifying an intra-block of M scalar SIMD instructions from the plurality of scalar SIMD instructions, wherein M>1;
- and
- translating the intra-block of M scalar SIMD instructions into N non-scalar SIMD instructions corresponding to the intra-block, wherein N<(M*4).
A system, comprising:
- a dynamic binary translator capable of:
- receiving a plurality of scalar single instruction multiple data stream (SIMD) instructions designed for a source architecture;
- identifying an intra-block of M scalar SIMD instructions from the plurality of scalar SIMD instructions, wherein M>1:
- and
- translating the intra-block of M scalar SIMD instructions into N non-scalar SIMD instructions for a target architecture, wherein N<(M*4);
- and
- an instruction execution mechanism capable of executing the N non-scalar SIMD instructions.
An article comprising a storage medium having stored thereon instructions that, when executed by a machine, result in the following:
- receiving a plurality of scalar single instruction multiple data stream (SIMD) instructions;
- identifying an intra-block of M scalar SIMD instructions from the plurality of scalar SIMD instructions, wherein M>1;
- and
- translating the intra-block of M scalar SIMD instructions into N non-scalar SIMD instructions with respect to a target architecture supporting parallel SIMD instructions, wherein N<(M*4).
A system comprising:
- a translator to receive a plurality of scalar single instruction multiple data stream (SIMD) instructions, and to identify an intra-block of M scalar SIMD instructions from the plurality of scalar SIMD instructions, wherein M<1;
- and
- an intra-block instruction translation mechanism in the translator, to generate N non-scalar SIMD instructions based on the M scalar SIMD instructions in the intra-block to produce a set of non-scalar SIMD instructions corresponding to the intra-block, wherein N<(M*4).
Dependencies are inferred from the claim text.