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US 7,249,339 B1Granted
Method and apparatus for optimizing delay paths through field programmable gate arrays
AssigneeAltera Corporation
InventorBruce Pedersen
Life of this patent
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Abstract
A method for improving a design on a field programmable gate array (FPGA) includes modifying the design in response to a unate characteristic of an input to a node on the FPGA, and rising and falling delays of a node feeding the input.
Claims26
A method for improving a design on a field programmable gate array (FPGA), comprising:
- modifying the design in response to a unate characteristic of an input to a node on the FPGA, and rising and falling delays of a node feeding the input in order to balance the rising and falling delays of the design.
A machine-readable medium having stored thereon sequences of instructions, the sequences of instructions including instructions which, when executed by a processor, causes the processor to perform:
- modifying a design on a field programmable gate array (FPGA) in response to a unate characteristic of an input to a node on the FPGA, and rising and falling delays of a node feeding the input in order to balance the rising and falling delays of the design.
A delay path optimization unit, comprising:
- an input characteristic unit that determines unate characteristics of inputs to nodes in a system;
- a delay value unit that determines rising and falling delay values of the nodes in the system;
- and
- a system modification unit that modifies the system in response to the unate characteristics of inputs to the nodes, and rising and falling delays of nodes feeding the inputs in order to balance the rising and falling delays of the system.
1 more element
Dependencies are inferred from the claim text.