Automatic wiring method for semiconductor integrated circuit, program for the same, and semiconductor integrated circuit

An automatic wiring method for a semiconductor integrated circuit used to form a semiconductor integrated circuit for performing a desired operation by laying out and interconnecting a plurality of macrocells, each implementing a given function, on a semiconductor chip, the method comprising:

• (a) a step of arranging a macrocell, in which a plurality of power terminals and a plurality of ground terminals are formed, on the semiconductor chip;
• (b) a step of forming a loop line group containing a first power line and a first ground line for supplying power to the macrocell along an outer frame of the macrocell;
• and
• (c) a step of connecting a corresponding one of the plurality of power terminals with the first power line that constitutes the loop line group via a second power line, and connecting a corresponding one of the plurality of ground terminals with the first ground line that constitutes the loop line group via a second ground line;
• wherein a given area, which is set away from the outer frame of the macrocell arranged on the semiconductor chip in the step (a) towards a center of the macrocell, is defined as a wiring limit area in which at least a part of the loop line group can be arranged.

A computer program product, in a computer readable medium, for automatic wiring of a semiconductor integrated circuit used to form a semiconductor integrated circuit for performing a desired operation by laying out and interconnecting a plurality of macrocells, each implementing a given function, on a semiconductor chip, the computer program product comprising:

• (a) instruction for arranging a macrocell, in which a plurality of power terminals and a plurality of ground terminals are formed on a line layer, on the semiconductor chip;
• (b) instruction for forming a loop line group containing a first power line and a first ground line for supplying power to the macrocell along an outer frame of the macrocell;
• and
• (c) instruction for connecting a corresponding one of the plurality of power terminals with the first power line through a second power line arranged on said line layer, and connecting a corresponding one of the plurality of ground terminals with the first ground line through a second ground line arranged on said line layer.

A computer program product, in a computer readable medium, for automatic wiring of a semiconductor integrated circuit used to form a semiconductor integrated circuit for performing a desired operation by laying out and interconnecting a plurality of macrocells, each implementing a given function, on a semiconductor chip, the computer program product comprising:

• (a) instruction for arranging a macrocell, in which a plurality of power terminals and a plurality of ground terminals are formed, on the semiconductor chip;
• (b) instruction for forming a loop line group containing a first power line and a first ground line for supplying power to the macrocell along an outer frame of the macrocell;
• and
• (c) instruction for connecting a corresponding one of the plurality of power terminals with the first power line that constitutes the loop line group via a second power line, and
• connecting a corresponding one of the plurality of ground terminals with the first ground line that constitutes the loop line group via a second ground line;
• wherein
• a given area, which is set away from the outer frame of the macrocell arranged on the semiconductor chip by the instruction (a) towards a center of the macrocell, is defined as a wiring limit area in which at least a part of the loop line group can be arranged.

A semiconductor integrated circuit for performing a desired operation in which a plurality of interconnected macrocells, each implementing a given function, are laid out on a semiconductor chip, wherein

• a plurality of power terminals and a plurality of ground terminals are formed in a macrocell,
• a loop line group containing a first power line for supplying power to the macrocell and a first ground line is formed along an outer frame of the macrocell,
• a corresponding one of the plurality of power terminals is connected with the first power line that constitutes the loop line group via a second power line, and a corresponding one of the plurality of ground terminals is connected with the first ground line that constitutes the loop line group via a second ground line, and
• a given area, which is set away front the outer frame of the macrocell towards a center of the macrocell, is defined as a wiring limit area in which at least a part of the loop line group can be arranged.

An automatic wiring method for performing a wiring layout using a multilayer line in an electronic computer, comprising:

• (a) a step of wiring a first constant potential line for transmitting a constant potential as a power source in an area outside of a macrocell;
• (b) a step of acquiring position information for a terminal disposed in the macrocell from a terminal library;
• and
• (c) a step of wiring a second constant potential line for connecting the first constant potential line and the terminal in the same line layer as the terminal based on the acquired position information.

A semiconductor integrated circuit comprising:

• a macrocell;
• a first constant potential line formed in an area outside the macrocell for transmitting a constant potential as a power source;
• a terminal disposed inside the macrocell and to which the constant potential is supplied;
• and
• a second constant potential line formed in the same line layer as the terminal, for connecting the first constant potential line with the terminal.

A computer program product, in a computer readable medium, for automatic wiring to perform a wiring layout using a multilayer line in an electronic computer, comprising:

• instruction for wiring a first constant potential line for transmitting a constant potential as a power source in an area outside of a macrocell;
• instruction for acquiring position information for a terminal disposed in the macrocell from a terminal library;
• and
• instruction for wiring a second constant potential line for connecting the first constant potential line and the terminal in the same line layer as the terminal based on the acquired position information.

An automatic wiring method for performing a wiring layout in an electronic computer, comprising:

• a step of acquiring a macrocell from a library and arranging the macrocell;
• a step of wiring a loop line group for transmitting a power supply voltage to the macrocell, at least a portion of the loop line group being located in a predefined area of the macrocell:
• a step of acquiring position information for a terminal disposed in the macrocell from a library;
• and
• a step of wiring a connection line for connecting the loop line group and the terminal based on the acquired position information.

A computer program product, in a computer readable medium, for automatic wiring to perform a wiring layout in an electronic computer, comprising:

• instruction for acquiring a macrocell from a library and arranging the macrocell;
• instruction for wiring a loop line group for transmitting a power supply voltage to the macrocell, at least a portion of the loop line group being located a predefined area of the macrocell;
• instruction for acquiring position information for a terminal disposed in the macrocell from a library;
• and
• instruction for wiring a connection line for connecting the loop line group and the terminal based on the acquired position information.

A semiconductor integrated circuit comprising:

• a macrocell in which a plurality of terminals is formed;
• a loop line group for transmitting power supply voltage to the macrocell, at least a portion of the loop line group being located in a predefined area of the macrocell;
• and
• a connection line for connecting the loop line group and the plurality of terminals.