Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores

#1. Technical Field

#The present invention relates to estimating power consumption in processor cores, and more particularly, to estimating power consumption when processing different workloads.

#2. Discussion of the Related Art

#FIG. 1 is a schematic diagram illustrating an exemplary embodiment of a computer system;

#FIG. 2 is a schematic diagram illustrating an exemplary embodiment of the present invention;

#FIG. 3 is a spreadsheet illustrating an exemplary embodiment of the present invention implemented as a spreadsheet;

#An exemplary embodiment of the present invention projects or estimates power dissipated by one or more processor cores, while processing an actual workload. This estimation can be accomplished by establishing reference power numbers for the processor core in question. These reference power numbers can be established by performing a detailed power analysis for reference test cases. Power for any new workload, also known as actual workload herein, is projected by relating the reference power number to the performance characteristics of the actual workload and the reference runs.

#The reference test cases, which are used to establish reference power, will be much smaller than the actual workloads that can be encountered in real deployments of the processor core. Hence, it will not be a problem for the analysis to complete without failures and in a reasonable time. The test cases will be chosen such that they cover the different architectural usage scenarios that actual workloads could exhibit. In contrast, if power has to be projected using one of the existing approaches, it will require the simulation and power analysis of every new workload in question using current tools. As mentioned above, this is not only time consuming, but also may not be practical for very long workloads.

#Referring to FIG. 1, according to an exemplary embodiment of the present invention, a computer system 101 for implementing the present invention includes a central processing unit (CPU) 102, a memory 103 and an input/output (I/O) interface 104. The computer system 101 is generally coupled through the I/O interface 104 to a display 105 and various input devices 106 such as a mouse and keyboard. The support circuits can include circuits such as cache, power supplies, clock circuits, and a communications bus. The memory 103 can include random access memory (RAM), read only memory (ROM), disk drive, tape drive, etc., or a combination thereof. The present invention can be implemented as a routine 107 that is stored in memory 103 and executed by the CPU 102 to process the signal from the signal source 108. As such, the computer system 101 is a general-purpose computer system that becomes a specific purpose computer system when executing the routine 107 of the present invention.