Single-burst-correction / double-burst-detection error code
AssigneeInternational Business Machines Corporation
InventorsRene Glaise, Arnaud Vangelisti
Life of this patent
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Abstract
A method and apparatus for performing encoding and decoding of bit chain data packets conveying errors which do not spread on more than n bits, at very high speed. In one embodiment, a matrix of the corresponding Systematic code is built using p×p matrix blocks comprising elements of a galois field, generated by an irreducible generator polynomial of degree p, p being greater or equal to n.
Claims14
A computer-implemented method for encoding a m-bit chain wherein the errors do not spread on more than n bits, n being lesser or equal to m, said method comprising:
- choosing an irreducible generator polynomial of degree p, p being greater or equal to n and such that m is lesser or equal to p(2p−1);
- building a matrix using 2p elements of the galois field (GF), generated by the generator polynomial, comprising the 2p−1 elements of the multiplicative group α0, α1, α2 . . . αp−1 and Ø, a null element for the addition and, using p×p blocks wherein the first line is one first element and the other lines are the other elements of the GF multiplicative group obtained by a circular permutation of the first line, in the following way:
- defining a first set of p columns comprising a succession of 2p+2 blocks wherein the first lines are respectively Ø, Ø and 2p times α0;
- defining a second set of p columns comprising a succession of 2p+2 blocks wherein the first lines are successively Ø, α0, Ø, α0, α1, α2 . . . αp−1;
- and
- defining a third set of p columns comprising a succession of 2p+2 blocks wherein the first lines are successively α0, Ø, Ø, α0, α0, (αp−1)−1, (αp−2)−1 . . . (α1)−1;
- and
- computing a bit chain code for the m-bit chain by performing a matrix multiplication of a bit chain wherein the m MSB bits are the m-bit chain and the remaining LSB bits are all-zero, by the previously built matrix and appending to the m-bit chain the bit chain code as new LSB bits.
A computer-implemented method for decoding a received bit chain wherein errors do not spread to more than n bits, said received bit chain comprising an m bit chain formed by the m MSB bits and a code bit chain formed by p remaining LSB bits, p being a degree of an irreducible generator polynomial, p being greater or equal to n such that m is lesser or equal to p(2p−1), said method comprising:
- building a matrix using 2p elements of the galois field (GF), generated by the generator polynomial comprising the 2p−1 elements of the multiplicative group, α0, α1, α2 . . . αp−1 and Ø, a null element for the addition and, using p×p blocks wherein the first line is one first element and other lines are the other elements of the GF multiplicative group obtained by a circular permutation of the first line, in the following way:
- defining a first set of p columns comprising a succession of 2p+2 blocks wherein the first lines are respectively Ø, Ø and 2p times α0;
- defining a second set of p columns comprising a succession of 2p+2 blocks wherein the first lines are successively Ø, α0, Ø, α0, α1, α2 . . . αp−1;
- and
- defining a third set of p columns comprising a succession of 2p+2 blocks wherein the first lines are successively α0, Ø, Ø, α0, α0, (αp−1)−1, (αp−2)−1 . . . (α1)−1;
- computing a syndrome bit chain for the received bit chain by performing a matrix multiplication of said received bit chain by the previously built matrix;
- and
- correcting errors introduced in one of the 2p−1×p bit sub chains forming the m MSB bits of the received bit chain by executing the following steps:
- performing a division in the GF, the divider being Sa, a p-bit chain formed by p MSB bits of the syndrome bit chain, the dividend being Sb, the following p MSB bits after Sa of the syndrome bit chain and obtaining an exact quotient p bit chain;
- using the exact quotient as a range of the p bit sub chain in the m MSB bits of the received bit chain to select a p bit sub chain containing errors;
- and
- taking Sa as an error pattern, changing a value of each bit of the selected p bit sub chain at a location identified by the bits in Sa which are set to 1.
Dependencies are inferred from the claim text.