Algorithm to test LPAR I/O subsystem's adherence to LPAR I/O firewalls
AssigneeInternational Business Machines Corporation
InventorsShakti Kapoor, Daljeet Maini
Life of this patent
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Abstract
A system for testing logical partitioning. In a preferred embodiment, an I/O adapter is configured to break partitioning rules, for example, to attempt to access addresses outside a valid address range. Software is used to check for expected errors at expected addresses. If expected errors are not found, a fault in the partitioning I/O subsystem is indicated.
Claims28
A method of testing direct memory access (DMA) in a logical partition system, comprising the steps of:
- configuring an I/O adapter to disobey one or more logical partition rules;
- and
- checking for expected errors at expected addresses, wherein the expected errors occur as a result of configuring the I/O adapter to disobey the one or more logical partition rules.
A method of finding a valid address range for an input/output (I/O) adapter in a computer system, comprising the steps of:
- (a) identifying a bus identification of the I/O adapter;
- (b) comparing the bus identification of the I/O adapter to a bus identification for a first PCI-to-host bridge in a device tree of the computer system;
- (c) if the comparing step of (b) determines that the first PCI-to-host bridge is not a parent of the I/O adapter, comparing the bus identification of the I/O adapter to bus identifications of PCI-to-PCI bridges that are children of the first PCI-to-host bridge to find a parent of the I/O adapter;
- (d) if the comparing step of (c) determines that none of the PCI-to-PCI bridges that are children of the first PCI-to-host bridge are parents of the I/O adapter, then repeating steps (b) and (c) for a second PCI-to-host bridge;
- and
- (e) when the parent of the I/O adapter is found, identifying the valid address range for the I/O adapter from a property of the parent.
A method of testing direct memory access (DMA) rules of a logical partition system, comprising the steps of:
- determining a valid address range for an input/output (I/O) adapter;
- attempting to access one or more addresses outside the valid address range with DMA, starting with a first address;
- if no DMA error occurs, logging the first address and reporting an error;
- if a DMA error occurs, comparing the first address to the DMA error address;
- and
- if the first address is not equal to the DMA error address, logging the first address and reporting an error.
A method of testing direct memory access (DMA) rules of a logical partition system, comprising the steps of:
- determining a valid address range for an input/output (I/O) adapter;
- configuring a DMA entity of the I/O adapter to throw one or more addresses outside the valid address range starting with a first address;
- after DMA is complete or an error occurs, comparing a last address thrown by the I/O adapter with the first address thrown by the I/O adapter;
- and
- if the last address is not the first address, reporting an error.
A method of testing direct memory access (DMA) rules of a logical partition system, comprising the steps of:
- determining a valid address range for an input/output (I/O) adapter;
- setting a size for a DMA operation such that the operation crosses the valid address range boundary into an invalid address range;
- detecting a first address on which a DMA error occurs during the DMA operation;
- and
- comparing the first address on which the DMA error occurs to a last address to which access is attempted.
A method of testing rules of a logical partition system, comprising the steps of:
- configuring an input/output (I/O) adapter with dual address cycle (DAC) on;
- triggering a direct memory access (DMA) operation for a valid address;
- and
- comparing the valid address with a DMA error address.
A system for testing direct memory access (DMA) in a logical partition system, comprising:
- an I/O adapter configured to disobey one or more logical partition rules;
- and
- an algorithm that checks for expected errors at expected addresses as a result of configuring the I/O adapter to disobey the one or more logical partition rules.
A computer program product for testing direct memory access (DMA) rules of a logical partition system, comprising the computer implemented steps of:
- first instructions for determining a valid address range for an input/output (I/O) adapter;
- second instructions for attempting to access one or more addresses outside the valid address range with DMA, starting with a first address;
- third instructions for, if no DMA error occurs, logging the first address and reporting an error;
- fourth instructions for, if a DMA error occurs, comparing the first address to the DMA error address;
- and
- fifth instructions for, if the first address is not equal to the DMA error address, logging the first address and reporting an error.
A system for testing direct memory access (DMA) rules of a logical partition system, comprising:
- means for determining a valid address range for an input/output (I/O) adapter;
- means for configuring a DMA entity of the I/O adapter to throw one or more addresses outside the valid address range starting with a first address;
- after DMA is complete or an error occurs, means for comparing a last address thrown by the I/O adapter with the first address thrown by the I/O adapter;
- and
- if the last address is not the first address, means for reporting an error.
Dependencies are inferred from the claim text.