US 7,249,301 B2Granted

Semiconductor circuit and method for testing, monitoring and application-near setting of a semiconductor circuit

AssigneeInfineon Technologies AG

InventorMartin Perner

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Abstract

A semiconductor circuit can have a standard interface for external data, address and/or command interchange in normal operation and a further test interface provided for a test operation with a semiconductor component and with a BIST unit (built-in self-test) assigned to the semiconductor component. The semiconductor circuit can also have a BIST controller for initialization, testing and application-near setting of the semiconductor component, a read-only nonvolatile memory, a programmable nonvolatile memory, and a volatile memory. The processed data stored as operating, test and/or boot parameters in the programmable nonvolatile memory are used during booting and in normal operation for test and configuration purposes for application-near setting of the semiconductor circuit.

Claims34

Dependent claims

A semiconductor circuit having a standard interface for external data, address or command interchange in normal operation and a test interface provided for a test operation, with a semiconductor memory and with a test control unit assigned to the semiconductor memory, comprising:

a controller for initialization, testing and application-near setting of the semiconductor memory in the normal operation;
a read-only nonvolatile memory, the read-only nonvolatile memory storing a standard program code for configuration and for testing of the semiconductor memory, standard test, and standard boot parameters;
a programmable nonvolatile memory, the programmable nonvolatile memory storing at least one further program code for configuration and for testing of the semiconductor memory, functional tests, operating parameters, test and boot parameters;
and
a volatile memory, the volatile memory being assigned to the controller, and during booting, an execution program code selected from the group including:
the standard program code and the at least one further program code being loaded for execution into the volatile memory, the controller performing a configuration during booting and optionally a testing of the semiconductor memory in subsequent normal operation by execution of functional tests and storing the data determined during testing as operating, test or boot parameters in the programmable nonvolatile memory or outputting the data externally via the standard interface or the test interface of the semiconductor circuit.

3 more elements

A method for testing, monitoring and application-near setting of a semiconductor circuit that uses a standard interface for external data, address or command interchange in a normal operation and a test interface for a test operation, with a semiconductor memory, comprising:

in response to the semiconductor circuit booting, interrogating boot-up flags stored in a programmable nonvolatile memory via a test control unit assigned to the semiconductor memory for configuration and test purposes, the boot-up flags including at least:
a start-up flag for determining whether a controller of the test control unit automatically boots and an execution program code flag for determining an execution program code selected from the group including:
a start program code from a read-only non-volatile memory and a further program code from the programmable non-volatile memory to be loaded by the controller into a volatile memory for execution, wherein each boot-up flag is assigned a boot-up sequence;
depending on the status of the start-up flag, determining a further start-up flag as to whether a controller of the test control unit automatically boots or does not boot;
depending on the status of the execution program code flag and in response to the controller booting, determining a further execution program code flag for determining an further execution program code selected from the group including:
a start program code from a read-only non-volatile memory and a further program code from the programmable non-volatile memory to be loaded by the controller into a volatile memory for execution, the further flags defining further boot-up flags;
in response to the controller booting, executing at least one boot-up sequence which is implemented in the execution program code and configures an operating mode of the semiconductor memory;
and
subsequent to the controller booting and being in normal operation, optionally initiating and executing functional tests provided in the execution program code.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/902,105Filed 30 Jul 2004
Priority: DE 103 34 80130 Jul 2003
Published: US 2005/0028058 A13 Feb 2005
Granted: 24 Jul 2007
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 29/1201
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: comprising I/O circuitry
G11C 29/16
Implementation of control logic, e.g. test mode decoders: using microprogrammed units, e.g. state machines
G11C 16/04
Electrically programmable: using variable threshold transistors, e.g. FAMOS
G11C 2029/0407
Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals: on power on