Integrated circuit device including a scan test circuit and methods of testing the same

A method for testing an integrated circuit device in which a plurality of associated macro blocks to be tested are configured for dynamic simulation testing, the method comprising:

• generating at a first sub logic circuit unit is of the macro blocks sub data for input to a plurality of input ports of a core block of the macro blocks responsive to data input to the first sub logic circuit unit core from external to the macro blocks;
• providing the sub data and/or output data for a plurality of output ports of the core block to a multiplexer (MUX) unit coupled between the core block and the first sub logic circuit that selectively provides the sub data or the output data as inputs to the input ports of the core block, without synchronizing the output data between the output ports of the core block and the MUX unit, responsive to a MUX control signal;
• and
• generating at the core block core output data for the output ports from the MUX input to the input ports of the core block.

A method for testing an integrated circuit device in which a core block of a plurality of associated macro blocks to be tested has a vector input terminal and is configured for scan testing and others of the associated macro blocks are configured for dynamic simulation testing, the method comprising:

• generating at a first sub logic circuit unit of the others of the associated macro blocks sub data for input to a plurality of input ports of the core block responsive to data input to the first sub logic circuit unit core from external to the macro blocks;
• providing the sub data and/or output data for a plurality of output ports of the core block to a multiplexer (MUX) unit coupled between the core block and the first sub logic circuit that selectively provides the sub data or the output data as inputs to the input ports of the core block, without synchronizing the output data between the output ports of the core block and the MUX unit, responsive to a MUX control signal;
• and
• generating at the core block core internal data responsive to the inputs to the input ports of the core block;
• outputting from the core block the core internal data during scan testing;
• and
• selectively generating at the core block core output data for the output ports responsive to the core internal data or to test vector serial input data from the vector input terminal.

A semiconductor device comprising:

• a first sub logic circuit unit which is designed to be adaptable for a dynamic simulation test method and generates sub data for each port by processing data received from the outside;
• a MUX unit which is controlled by a MUX control signal and selectively outputs the sub data for each port or core output data for each port;
• a core block which is designed to be adaptable for the dynamic simulation test method and generates the core output data for each port by processing the output data for each port received from the MUX unit, wherein the MUX unit selectively outputs the core output data for each port without synchronizing the core output data between output ports of the core block and the MUX unit;
• and
• a second sub logic circuit unit which is designed to be adaptable for the dynamic simulation test method and outputs final output data to the outside by processing the core output data for each port received from the core block.

A semiconductor device comprising:

• a first sub logic circuit unit which is designed to be adaptable for a dynamic simulation test method and generates sub data for each port by processing data received from the outside;
• a MUX unit which is controlled by a MUX control signal and selectively outputs the sub data for each port or core output data for each port;
• a core block which generates core internal data by processing the output data for each port received from the MUX unit and outputs the core internal data for each port to the outside by using a scan test method or generates the core output data for each port by selectively processing the core internal data for each port or serial input data for each port used as a test vector, wherein the MUX unit selectively outputs the core output data for each port without synchronizing the core output data between output ports of the core block and the MUX unit;
• and
• a second sub logic circuit unit which is designed to be adaptable for the dynamic simulation test method and outputs final output data to the outside by processing the core output data for each port received from the core block.

A test method of a semiconductor device in which all macro blocks are designed to be adaptable for a dynamic simulation test method, the test method comprising:

• generating sub data for each port by processing data received from the outside, at a first sub block included in the macro blocks;
• selectively outputting the sub data for each port or core output data for each port, at a MUX included in the macro blocks and controlled by a MUX control signal, without synchronizing the core output data for each port between output ports of a core block included in the macro blocks and the MUX;
• generating the core output data for each port by processing the output data for each port received from the MUX, at the core block included in the macro blocks;
• and
• outputting final output data to the outside by processing the core output data for each port received from the core block, at a second sub block included in the macro blocks.

A test method of a semiconductor device in which a core block of macro blocks is designed to be adaptable for a scan test method and other blocks of the macro blocks are designed to be adaptable for a dynamic simulation test method, the test method comprising:

• generating sub data for each port by processing data received from outside, at a first sub block included in the other blocks of the macro blocks;
• selectively outputting the sub data for each port or core output data for each port, at a MUX included in the other blocks of the macro blocks and controlled by a MUX control signal, without synchronizing the core output data for each port between output ports of the core block and the MUX;
• generating core internal data for each port by processing the output data for each port received from the MUX or generating the core output data for each port by selectively processing the core internal data for each port or serial input data used as a test vector received from outside, at the core block included in the macro blocks;
• and
• outputting final output data to the outside by processing the core output data for each port received from the core block, at a second sub block included in the other blocks of the macro blocks.