Multiple scan chains with pin sharing
AssigneeSamsung Electronics Co., Ltd.
InventorGyoochan Sim
Life of this patent
Estimating the term…
Abstract
A scan based design architecture reduces pin count, test time and power consumption, and also allows the use of existing verified scan vectors by driving multiple scan chains from one scan input and utilizing multiple scan clocks. The scan vectors for multiple scan chains are sequentially applied to the scan input so as to broadcast the vectors to multiple scan chains, but only the bits for one scan chain are selectively clocked into that chain by a corresponding one of the multiple scan clocks. An output multiplexer can also be used to reduce the total number of test pins. The pin count can be further reduced by using a scan clock generator to generate the multiple scan clocks from a single scan clock input, and by using a select signal generator to generate select signals that control an output multiplexer.
Claims37
A circuit comprising a plurality of scan chains having a plurality of scan inputs coupled to an input terminal, and a plurality of scan clock inputs coupled to receive a plurality of scan clock signals, wherein at least two of the scan inputs are connected together at a single input terminal, and wherein data for more than one of the scan chains are sequentially applied to the single input terminal and clocked by corresponding ones of the scan clock signals so that data for a first one of the scan chains is interleaved with data for at least a second one of the scan chains.
A circuit comprising a plurality of scan chains having a plurality of scan outputs coupled to an output terminal through a multiplexer, wherein the multiplexer output is transmitted to the output terminal without passing through a partitioning scan chain, and wherein the plurality of scan chains have a plurality of scan inputs coupled to a single input terminal, and a plurality of scan clock inputs coupled to receive a plurality of scan clock signals, and wherein the circuit is arranged so that data for more than one of the scan chains is sequentially applied to the single input terminal and clocked by corresponding ones of the scan clock signals so that data for a first one of the scan chains is interleaved with data for at least a second one of the scan chains.
A circuit comprising a plurality of scan chains having a plurality of scan outputs coupled to an output terminal through a multiplexer, wherein the multiplexer output is transmitted to the output terminal without passing through a partitioning scan chain, and wherein:
- each of the scan chains comprises a plurality of level sensitive scan design elements;
- the plurality of scan clock inputs are master scan clock inputs;
- the plurality of scan clock signals are master scan clock signals;
- and
- the plurality of scan chains have a plurality of slave clock inputs coupled to receive a plurality of slave scan clock signals.
A method for testing a circuit comprising a plurality of scan chains having a plurality of scan inputs and a plurality of scan outputs, the method comprising:
- driving the plurality of scan inputs through an input terminal, wherein at least two of the scan inputs receive the same scan input signal;
- and
- clocking the plurality of scan chains with a plurality of scan clock signals;
- wherein data for more than one of the scan chains are sequentially applied to the single input terminal and clock by corresponding ones of the scan clock signals so that data for a first one of the scan chains is interleaved with data for at least a second one of the scan chains.
A method for testing a circuit comprising a plurality of scan chains having a plurality of scan inputs and a plurality of scan outputs, the method comprising;
- driving the plurality of scan inputs through an input terminal, wherein at least two of the scan inputs receive the same scan input signal, and data for more than one of the scan chains are sequentially applied to the input terminal;
- clocking the plurality of scan chains with corresponding ones of a plurality of scan clock signals, so that data for a first one of the scan chains is interleaved with data for at least a second one of the scan chains;
- and
- shifting out data from the plurality of scan outputs through a multiplexer to an output terminal.
A method for loading scan vectors into a circuit comprising a plurality of scan chains having a plurality of scan inputs and a plurality of scan outputs, the method comprising:
- broadcasting a plurality of scan vectors to the plurality of scan chains wherein bits from more than one of the scan vectors are interleaved;
- and
- selectively clocking only the bits of a first one of the scan vectors into a first one of the scan chains.
Dependencies are inferred from the claim text.