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US 7,249,296 B2Granted
Semiconductor integrated circuit
AssigneeKabushiki Kaisha Toshiba
InventorOsamu Hirabayashi
Life of this patent
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Abstract
An ECC circuit has an error correction function of N (N is a natural number) bits for output data of a memory cell array. A BIST circuit reads background data out of test target addresses, and writes/reads inverted data of the background data in at least a part of the testing target addresses. An N+1 bit error detection circuit outputs a signal indicative of test NG (defective product) when a total of error bit numbers n1 and n2 detected by the ECC circuit during first and second readings exceeds N.
Claims19
A semiconductor integrated circuit comprising:
- a memory;
- an ECC circuit that has an error correction function of N (N is a natural number) bits for output data of the memory;
- an error detection circuit configured to output a signal indicative of the following fact, if a total of an error bit number n1 detected by the ECC circuit when a first data pattern in testing target addresses of the memory is read out and an error bit number n2 detected by the ECC circuit when a second data pattern that is an inversion of the first data pattern in at least a part of the testing target addresses is read out exceeds N;
- and
- a BIST circuit configured to read the first data pattern out of the testing target addresses of the memory as a first operation,
- write the second pattern in at least a part of the testing target addresses as a second operation, and
- read out the written second data pattern,
- wherein the first data pattern has been corrected by the ECC circuit and is input to the BIST circuit.
5 more elements
A test method of a semiconductor memory with an ECC circuit comprising:
- reading a first data pattern out of testing target addresses of a memory;
- detecting an error bit number n1 by using the ECC circuit that has an error correction function of N (N is a natural number) bits;
- writing/reading a second data pattern that is an inversion of the first data pattern in at least a part of the testing target addresses;
- detecting an error bit number n2 by using the ECC circuit;
- and
- determining whether a total of the error bit numbers n1 and n2 exceeds N or not.
3 more elements
Dependencies are inferred from the claim text.