Semiconductor memory device with reduced package test time

A semiconductor memory device comprising:

• first and second package option pads wire-bonded with pins as a default package option;
• a buffer control signal generation means for generating a buffer control signal;
• a first buffering means for, in a normal mode, buffering a first signal applied to the first package option pad in response to the buffer control signal and outputting the buffered first signal as a first package option signal, and in a test mode, blocking the first applied signal and outputting a signal corresponding to a signal other than the first applied signal as the first package option signal;
• and
• a second buffering means for, in a normal mode, buffering a second signal applied to the second package option pad in response to the buffer control signal and outputting the buffered second signal as a second package option signal, and in a test mode, blocking the second applied signal and outputting a signal corresponding to a signal other than the second applied signal as the second package option signal.

A semiconductor memory device comprising:

• at least one package option pad wire-bonded with pins as a default package option;
• a buffer control signal generation means for generating a buffer control signal;
• a buffering means for buffering signals applied to the at least one package option pad;
• and
• a switching means for, in response to the buffer control signal, transferring an output of the buffering means and a signal corresponding to package options, other than the default package options, as a package option signal.