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US 7,249,293 B2Granted
Method and device for testing for the occurrence of bit errors
AssigneeFujitsu Limited
InventorNaonori Nishioka
Life of this patent
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AssigneeFujitsu Limited
InventorNaonori Nishioka
Estimating the term…
In a method and a device for testing a plurality of measured devices in parallel by using a single signal generator and a single bit error measuring device, a serial testing signal for is converted and demultiplexed into parallel signals corresponding to channels respectively assigned to a plurality of measured devices and a redundant channel, one of the plurality of parallel signals being a passing signal passing through the redundant channel is converted into a channel determination signal for specifying an alignment of the measured devices, output signals of the measured devices and the channel determination signal are multiplexed corresponding to a demultiplexing mode used for demultiplexing the serial signal, and bit errors are measured in the multiplexed signals and measured devices at which the bit errors are generated are detected in consideration of the channel determination signal.
A method for detecting a device which causes a bit reversal when the device is in trouble, comprising:
An apparatus for detecting a device which causes a bit reversal when the device is in trouble, comprising:
An apparatus for detecting a device which causes a bit reversal when the device is in trouble comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
By comparing a transmitted test signal with a locally generated replica: test sequence generators
Using signal quality detector: details of error rate determination, e.g. BER, FER or WER
Digital communication
Term ended 24 Sep 2021 (estimated)
1. Field of the Invention
The present invention relates to a method and a device for testing for the occurrence of bit errors, and in particular to a method and a device for conducting a test for the occurrence of bit errors in a plurality of communication devices.
2. Description of the Related Art
The above and other objects and advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which the reference numerals refer to like parts throughout and in which:
FIG. 1 is a block diagram exemplifying a time division demultiplexing/multiplexing parallel measurement system in a method and a device for testing for the occurrence of bit errors according to the present invention;
FIG. 2 is a block diagram showing a method and a device for testing for the occurrence of bit errors according to the present invention in which a configuration of determining a channel location is included in the measurement system shown in FIG. 1;
FIG. 5 shows a specific embodiment of a method and a device for testing for the occurrence of bit errors according to the present invention shown in FIGS. 1 and 2.
In this embodiment, the signal generator 1 shown in FIG. 5 generates a testing signal S of 2.4G (b/s). The signal demultiplexer 2 has an S/P (serial/parallel) converter with 16 output channels. Specifically, 1-15 channels are assigned to modules 3-1-3-15 as the measured devices and the 16th channel (CH16) is assigned to the all bit error generating circuit 6 as the channel determination signal generating circuit.
In this embodiment, since the measured modules 3-1-3-15 perform an optoelectro conversion (O/E), serial circuits of master optical modules M1-M15 which perform electrooptic conversion (E/O) and optical power adjusters ATT1-ATT15 are respectively inserted into the preceding stages of the measured modules 3-1-3-15.