Deskew circuit and disk array control device using the deskew circuit, and deskew method
AssigneeHitachi, Ltd.
InventorsYuji Takei, Seiichi Abe
Life of this patent
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Abstract
A deskew circuit includes, for clock and every bit of data, a variable delay circuit between a receiver that receives data and a flip-flop that first latches the data, in which a detecting pattern to detect a stable region for receiving data is repeatedly sent before implementing a data transfer, a delay value with which the starting edge an ending edge of the data match the rising edge of the clock is found for the variable delay circuit, and a delay value with which the transfer data can be received in a stable manner is set based on the delay value of the variable delay circuit.
Claims12
A disk array control device comprising:
- a channel adapter connected to a host computer,
- said channel adapter comprises;
- a channel control circuit receiving data from said host computer, and
- a deskew circuit receiving said data from said channel control circuit,
- wherein said deskew circuit comprises:
- a first receiver that receives data and is provided for each bit of a data bus composed of a plurality of bits,
- a first variable delay circuit that is provided with an output of the first receiver,
- a second receiver that receives a clock transferred in parallel with the data,
- a second variable delay circuit that is provided with an output of the second receiver,
- a first delay circuit that gives a first delay to an output of the second variable delay circuit, and
- a second delay circuit that gives a delay greater than the first delay to the output of the second variable delay circuit.
A method of controlling a disk array which includes a channel adapter connected to a host computer, said method comprising the steps of:
- receiving by a channel control circuit data from said host computer;
- and
- receiving by a deskew circuit said data from said channel control circuit,
- wherein said deskew circuit comprises:
- a first receiver that receives data and is provided for each bit of a data bus composed of a plurality of bits,
- a first variable delay circuit that is provided with an output of the first receiver,
- a second receiver that receives a clock transferred in parallel with the data,
- a second variable delay circuit that is provided with an output of the second receiver,
- a first delay circuit that gives a first delay to an output of the second variable delay circuit, and
- a second delay circuit that gives a delay greater than the first delay to the output of the second variable delay circuit.
A disk array control device comprising:
- a deskew circuit receiving data from a host computer coupled to said disk array control device,
- wherein said deskew circuit comprises:
- a first receiver that receives date and is provided for each bit of a data bus composed of a plurality of bits,
- a first variable delay circuit that is provided with an output of the first receiver,
- a second receiver that receives a clock transferred in parallel with the data,
- a second variable delay circuit that is provided with an output of the second receiver,
- a first delay circuit that gives a first delay to an output of the second variable delay circuit, and
- a second delay circuit that gives a delay greater than the first delay to the output of the second variable delay circuit.
A method of controlling a disk array control device comprising the steps of:
- receiving by a deskew circuit data from a host computer coupled to said disk array control device,
- wherein said deskew circuit comprises:
- a first receiver that receives data and is provided for each bit of a data bus composed of a plurality of bits,
- a first variable delay circuit that is provided with an output of the first receiver,
- a second receiver that receives a clock transferred in parallel with the data,
- a second variable delay circuit that is provided with an output of the second receiver,
- a first delay circuit that gives a first delay to an output of the second variable delay circuit, and
- a second delay circuit that gives a delay greater than the first delay to the output of the second variable delay circuit.
Dependencies are inferred from the claim text.