System and method for scalable clock gearing mechanism
AssigneeIntel Corporation
InventorDarrell S. McGinnis
Life of this patent
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Abstract
In some embodiments, a system and method for making a scalable clock gearing mechanism may allow multiple devices operating on different clock speeds to communicate. In an embodiment, a mechanism may be used to input data clocked on a first clock frequency and output the data on a second clock frequency. The mechanism may temporarily store the data until the next clock cycle of the second clock. Further, the mechanism may make use of multiple inputs or outputs to input or output multiple data units during a single clock cycle to keep the delay between the arrival and departure of the data small.
Claims17
A method, comprising:
- identifying a source clock frequency having a source clock period;
- identifying a destination clock frequency having a destination clock period;
- identifying a clock gearing ratio corresponding to the source and destination clock frequencies;
- receiving a source data stream at the source clock frequency, wherein the data stream is comprised of a plurality of source data units;
- providing the source data stream as a destination data stream at the destination clock frequency;
- and
- providing the destination data stream on a plurality of data outputs such that each received source data unit is provided as a destination data unit in the next destination clock period.
A method comprising:
- identifying a source clock frequency having a source clock period;
- identifying a destination clock frequency having a destination clock period;
- identifying a clock gearing ratio corresponding to the source and destination clock frequencies;
- receiving a source data stream at the source clock frequency, wherein the data stream is comprised of a plurality of source data units;
- providing the source data stream as a destination data stream at the destination clock frequency;
- and
- outputting a first received source data unit and a second received source data unit as a first destination data unit and a second destination data unit in the next available destination clock period on a first destination output and a second destination output.
A system, comprising:
- a first data input for receiving input data clocked by a source clock;
- a first output selector adapted to direct selected received input data to a first output as first output data;
- a second output selector adapted to direct selected received input data to a second output as second output data;
- a first clock gear register adapted to control the first output selector;
- a second clock gear register adapted to control the second output selector;
- wherein the first and second clock gear registers provide data representative of the destination clock periods in which data is output to the first and second outputs.
Dependencies are inferred from the claim text.