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US 7,249,273 B2Granted
Synchronized serial interface
AssigneeIntel Corporation
InventorsChengting Zhao, Ashish Gupta, Edward R. Helder, Fangxing Wei
Life of this patent
Estimating the term…
Abstract
Some embodiments provide a synchronization circuit to receive a synchronization signal, the synchronization signal substantially synchronized with a data transition, to synchronize the synchronization signal with a clock signal, and to generate a load signal based on the synchronized synchronization signal. Also provided may be a ring counter to receive the load signal from the synchronization circuit and to circularly propagate the load signal.
Claims27
A device comprising:
- a synchronization circuit to receive a synchronization signal, the synchronization signal substantially synchronized with a data transition, to synchronize the synchronization signal with a clock signal, and to generate a load signal based on the synchronized synchronization signal;
- and
- a ring counter to receive the load signal from the synchronization circuit and to circularly propagate the load signal;
- and
- a multiplexer to receive a plurality of delayed load signals from the ring counter, to receive an offset signal, and to output one of the plurality of delayed load signals based on the offset signal.
2 more elements
A device comprising:
- a synchronization circuit to receive a synchronization signal, the synchronization signal substantially synchronized with a data transition, to synchronize the synchronization signal with a clock signal, and to generate a load signal based on the synchronized synchronization signal;
- a ring counter to receive the load signal from the synchronization circuit and to circularly propagate the load signal;
- and
- an enabling circuit to assert and to deassert an enable signal,
- wherein the ring counter is to receive the enable signal, to receive the load signal from the synchronization circuit if the enable signal is asserted, and to circularly propagate the load signal if the enable signal is deasserted.
2 more elements
A device comprising:
- a synchronization circuit to receive a synchronization signal, the synchronization signal substantially synchronized with a data transition, to synchronize the synchronization signal with a clock signal, and to generate a load signal based on the synchronized synchronization signal;
- a ring counter to receive the load signal from the synchronization circuit and to circularly propagate the load signal, wherein the ring counter comprises one or more delay elements to receive the load signal, to delay the load signal, and to output the delayed load signal, the clock signal to reflect a clock period, and each of the one or more delay elements to delay the load signal for a respective period substantially equal to an integer multiple of the clock period;
- and
- a multiplexer to receive a delayed load signal from a plurality of the one or more delay elements, to receive an offset signal, and to output one of the received delayed load signals based on the offset signal.
1 more element
A device comprising:
- a synchronization circuit to receive a synchronization signal, the synchronization signal substantially synchronized with a data transition, to synchronize the synchronization signal with a clock signal, and to generate a load signal based on the synchronized synchronization signal;
- a ring counter to receive the load signal from the synchronization circuit and to circularly propagate the load signal;
- and
- a multiplexer to receive the load signal from the synchronization circuit, to receive a circularly propagating load signal from the ring counter, to receive an enable signal, to output the received load signal to the ring counter if the enable signal is asserted, and to output the circularly propagating load signal to the ring counter if the enable signal is deasserted.
1 more element
A device comprising:
- a synchronization circuit to receive a synchronization signal, the synchronization signal substantially synchronized with a data transition, to synchronize the synchronization signal with a clock signal, and to generate a load signal based on the synchronized synchronization signal;
- a ring counter to receive the load signal from the synchronization circuit and to circularly propagate the load signal;
- and
- wherein the synchronization circuit comprises:
- a delay element to delay the synchronized synchronization signal;
- an inverter to invert the delayed synchronized synchronization signal;
- and
- a logic element to AND the delayed inverted signal and the synchronized synchronization signal, and to output the load signal.
5 more elements
A method comprising:
- receiving a synchronization signal, the synchronization signal substantially synchronized with a data transition;
- synchronizing the synchronization signal with a clock signal;
- generating a load signal based on the synchronized synchronization signal, the load signal including a load pulse;
- inputting the load signal into a ring counter of one or more delay elements, a time for the load pulse to propagate completely through the ring counter being substantially equal to a minimum data transition period;
- and
- outputting the load signal from a first node of the ring counter, a period between successive outputs of the load pulse being substantially equal to the data transition period.
3 more elements
A device to:
- receive a synchronization signal, the synchronization signal substantially synchronized with a minimum data transition period;
- synchronize the synchronization signal with a clock signal;
- generate a load signal based on the synchronized synchronization signal, the load signal including a load pulse;
- input the load signal into a ring counter of one or more delay elements, a time for the load pulse to propagate completely through the ring counter being substantially equal to the minimum data transition period;
- and
- output the load signal from a first node of the ring counter, a period between successive outputs of the load pulse being substantially equal to the minimum data transition period.
3 more elements
A system comprising:
- a memory controller hub comprising:
- a synchronization circuit to receive a synchronization signal, the synchronization signal substantially synchronized with a data transition, to synchronize the synchronization signal with a clock signal, and to generate a load signal based on the synchronized synchronization signal;
- a ring counter to receive the load signal from the synchronization circuit and to circularly propagate the load signal;
- and
- a parallel-to-serial converter to generate serial data based on the load signal;
- and a double data rate memory to receive the serial data.
3 more elements
Dependencies are inferred from the claim text.