Method for performing performance optimization operations for a processor having a plurality of processor cores in response to a stall condition
AssigneeIntel Corporation
InventorDileep P. Bhandarkar
Life of this patent
Estimating the term…
Abstract
Apparatus and method to make the most use possible of available capacities for the supply of power to and/or the dissipation of heat from a plurality of processor cores through responding to stalls in one or more of the processor cores among the plurality of processor cores by placing stalled processor cores into a lower power state and increasing the voltage and/or power of the remaining processor cores, and by decreasing the voltage and/or power of the remaining processor cores and taking stalled processor cores out of a lower power state when a condition causing a stall has ceased.
Claims11
A method comprising:
- in a processing system with a processor having a plurality of processor cores in which all of the processor cores are operating at a first voltage and a first frequency and at least one of the processor cores is not idle but is executing a command that has caused a stall condition, performing performance optimization operations in response to the stall condition, the performance optimization operations comprising:
- placing the processor core that is executing the command that caused the stall condition into a lower power state;
- checking data concerning maximum values for clock frequency and power supply voltage to be provided to the processor, wherein the data concerning maximum values comprises a table with multiple entries, wherein each entry lists a predetermined voltage and corresponding predetermined frequency determined to be suitable when a specified number of processor cores is in the lower power state, and wherein the operation of checking the data comprises using the table to determine a suitable voltage and corresponding frequency, based on a current number of processor cores in the lower power state;
- and
- increasing frequency and voltage of at least one non-stalled processor core, based on the entry in the table for the current number of processor cores in the lower power state;
- after increasing frequency and voltage of at least one non-stalled processor core, responding to termination of the stall condition by performing operations comprising:
- decreasing frequency and voltage of at least one non-stalled processor core;
- and
- taking the processor core for which the stall condition has terminated out of the lower power state.
A machine-accessible medium comprising code that when executed by a processor having a plurality of processor cores within an electronic system, causes the processor to:
- when all of the processor cores are operating at a first voltage and a first frequency and at least one of the processor cores is not idle but is executing a command that has caused a stall condition, performing performance optimization operations in response to the stall condition, the performance optimization operations comprising:
- placing the processor core that is executing the command that caused the stall condition into a lower power state;
- checking data concerning maximum values for clock frequency and power supply voltage to be provided to the processor, wherein the data concerning maximum values comprises a table with multiple entries, wherein each entry lists a predetermined voltage and corresponding predetermined frequency determined to be suitable when a specified number of processor cores is in the lower power state, and wherein the operation of checking the data comprises using the table to determine a suitable voltage and corresponding frequency, based on a current number of processor cores in the lower power state;
- and
- increasing frequency and voltage of at least one non-stalled processor core of the processor, based on the entry in the table for the current number of processor cores in the lower power state;
- after increasing frequency and voltage of at least one non-stalled processor core, responding to termination of the stall condition by performing operations comprising:
- decreasing frequency and voltage of at least one non-stalled processor core;
- and
- taking the processor core for which the stall condition has terminated out of the lower power state.
Dependencies are inferred from the claim text.